Multigate Source-Drain Airgap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing multigate device fabrication technologies face challenges such as increased parasitic capacitance, contact resistance, and short-channel effects, which hinder the development of high-performance and low-power integrated circuits.
Innovation Solution
The fabrication method involves forming multigate devices with optimized source/drain features, including bar-like or lollipop-like profiles and air gaps, along with tailored semiconductor layer stacks and gate structures to reduce parasitic capacitance and contact resistance, while maintaining effective gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional fabrication technologies are used for multigate devices, then manufacturing process simplicity is maintained, but parasitic capacitance increases
Solution Approach 1:
The patent introduces air gaps in the vertical dimension between source/drain features and adjacent structures. This dimensional approach creates electrical isolation that reduces parasitic capacitance without complicating the horizontal fabrication process layout, thereby resolving the contradiction between process simplicity and capacitance reduction.
Solution Approach 2:
The patent applies selective removal of semiconductor material only in specific local regions to create air gaps, rather than modifying the entire structure. This localized approach reduces parasitic capacitance at critical interfaces while maintaining the overall simplicity of the fabrication process for the rest of the device.
2Ease of manufacture
If conventional source/drain structures are used, then manufacturing is simplified, but contact resistance increases
Solution Approach 1:
The patent creates elevated or recessed source/drain structures by removing material in the vertical dimension, forming air gaps that improve contact interfaces. This dimensional modification enhances electrical contact reliability without requiring complex lateral processing steps, thus maintaining manufacturing simplicity while reducing contact resistance.
Solution Approach 2:
The patent performs selective material removal to create air gaps and optimized contact interfaces before final metallization and contact formation steps. This preliminary structuring prepares the surface for better contact formation, reducing contact resistance while keeping the overall manufacturing process straightforward.
3Productivity
If channel width is reduced to increase packing density, then transistor packing density improves, but short-channel effects worsen
Solution Approach 1:
The patent introduces vertical air gaps and multi-layer channel structures that provide electrostatic control in the vertical dimension. This allows the gate to effectively control the channel even when the horizontal channel width is reduced for higher packing density, thereby mitigating short-channel effects while maintaining high transistor density.
Solution Approach 2:
The patent employs multi-layer semiconductor structures where channels are nested vertically with air gaps between layers. This nested configuration allows multiple channels to be stacked in the vertical direction, increasing effective channel width and packing density while each individual channel maintains sufficient dimensions to avoid severe short-channel effects.
Data Source
AI summary
Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition; patterning the semiconductor stack to form a semiconductor fin; forming a dielectric fin next to the semiconductor fin; forming a first gate stack on the semiconductor fin and the dielectric fin; etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess; and epitaxially growing a source/drain feature in the source/drain recess, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin.