Multi-Gate Source/Drain Epitaxy for Lower Leakage and Contact Resistance
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Solution Overview
Problem
Conventional epitaxial features in multi-gate transistors, such as MBC transistors, are inadequate in reducing leakage, capacitance, and resistance, leading to suboptimal performance.
Innovation Solution
The method involves forming source/drain features with a shielding epitaxial layer covering undoped semiconductor features and sidewalls, followed by a heavily doped epitaxial layer spaced apart by the shielding layer, and a capping epitaxial layer to reduce void formation and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial features are used in multi-gate transistors, then the device structure is simple and manufacturing is easier, but leakage is not sufficiently reduced, capacitance remains high, and resistance is not optimized
Solution Approach 1:
The source/drain region is divided into multiple epitaxial layers with distinct functions: a first epitaxial layer for leakage reduction, a second epitaxial layer for resistance reduction, and a third epitaxial layer for capacitance reduction. This segmentation allows each layer to be optimized independently for its specific function, resolving the contradiction between improving reliability and managing device complexity.
Solution Approach 2:
Different epitaxial layers are assigned different doping concentrations and material compositions tailored to specific locations and functions within the source/drain region. The first layer uses one doping concentration for leakage control, while the second layer uses a different doping concentration for resistance optimization, implementing local quality to simultaneously address multiple performance parameters.
2Manufacturing precision
If the heavily doped epitaxial layer is deposited directly on the undoped semiconductor feature, then the manufacturing process is simpler, but void formation occurs and contact resistance increases
Solution Approach 1:
The first epitaxial layer is deposited beforehand as an intermediate layer between the undoped semiconductor feature and the heavily doped second epitaxial layer. This preliminary action prevents direct contact that would cause void formation, ensuring proper adhesion and eliminating manufacturing defects before the heavily doped layer is deposited.
Solution Approach 2:
The first epitaxial layer serves as an intermediary layer between the undoped semiconductor feature and the heavily doped second epitaxial layer. This intermediate layer facilitates proper adhesion and prevents void formation by providing a transition interface, thereby reducing contact resistance without significantly increasing process complexity.
3Reliability
If the epitaxial layers are made thinner to reduce capacitance, then capacitance is reduced, but leakage reduction effectiveness decreases
Solution Approach 1:
The epitaxial structure is segmented into multiple layers, allowing the first epitaxial layer to be optimized for leakage reduction while the third epitaxial layer is optimized for capacitance reduction. This segmentation enables each layer to have different thicknesses tailored to its specific function, resolving the contradiction between leakage reduction and capacitance reduction.
Solution Approach 2:
Different regions of the epitaxial structure have different thicknesses and compositions: the first epitaxial layer has a thickness optimized for leakage control, while the third epitaxial layer has a different thickness optimized for capacitance reduction. This local quality approach allows simultaneous optimization of both parameters without compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces void formation in source/drain features and contact resistance, enhancing the performance of multi-gate transistors by maximizing the volume of the highly doped epitaxial layer.
Implementation Method 1
selectively depositing a shielding epitaxial layer on sidewalls of the plurality of channel layer and surfaces of the undoped semiconductor layer
Implementation Method 2
depositing a heavily doped epitaxial layer over the shielding epitaxial layer and the inner spacers
Implementation Method 3
depositing a capping epitaxial layer over the heavily doped epitaxial layer
Data Source
AI summary
Methods and semiconductor structures are provided. A method according to the present disclosure includes forming, over a substrate, a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess that extends into the substrate and exposes a portion of the substrate, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively forming a buffer semiconductor layer on the exposed portion of the substrate, selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layer and the buffer semiconductor layer such that a top surface of the buffer semiconductor layer is completely covered by the first epitaxial layer, and depositing a second epitaxial layer over the first epitaxial layer and the inner spacers.