Multi-Gate Source/Drain Gap Formation for Leakage Control
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Solution Overview
Problem
Multi-gate transistors, particularly multi-bridge-channel (MBC) transistors, face issues with limited gate control over the mesa due to the gate structure engaging only the top surface, leading to potential leakage paths and performance degradation from source/drain feature configurations.
Innovation Solution
A method involving the formation of fin-shaped structures with interleaved sacrificial and channel layers, followed by recessing and deposition of dielectric and polymer layers to create inner spacer features, allowing epitaxial growth of source/drain features that are vertically spaced apart from the substrate, thereby reducing leakage and controlling resistive-capacitive delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source/drain features are allowed to contact the mesa, then manufacturing simplicity is improved, but leakage current increases
Solution Approach 1:
The patent introduces an intermediary structure (isolation dielectric material) between the source/drain features and the mesa to prevent direct contact. This mediator blocks the leakage path while allowing the source/drain features to be formed using standard epitaxial processes, thus resolving the contradiction between manufacturing simplicity and leakage prevention.
2Device complexity
If gate structure engages only the top surface of the mesa, then device fabrication is simplified, but gate control is reduced
Solution Approach 1:
The patent extends the gate structure from merely top-surface engagement to wrap-around configuration that contacts the mesa sidewalls. This dimensional extension (from 2D top contact to 3D wrap-around contact) enhances gate control over the channel and mesa region without significantly complicating the fabrication process, as the wrap-around structure is formed through conformal deposition techniques.
3Object-generated harmful factors
If source/drain features are vertically spaced apart from the substrate, then leakage is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the isolation dielectric material and defining the gap region before final source/drain feature formation. The inner spacer structures are also preliminarily formed to define the vertical spacing. These preliminary structures are then removed or integrated, leaving the desired gap. This sequence achieves leakage reduction through vertical spacing while managing manufacturing complexity through a systematic multi-step process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes leakage current and optimizes source/drain feature configurations, enhancing the performance of MBC transistors by reducing contact resistance and parasitic capacitance.
Implementation Method 1
depositing a polymer layer over the dielectric layer
Implementation Method 2
etching back the polymer layer and the dielectric layer
Implementation Method 3
epitaxially depositing more than one epitaxial layer from the sidewalls of the plurality of channel layers to form a source/drain feature
Data Source
AI summary
Multi-gate transistor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a fin-shaped structure over a substrate and including channel layers interleaved by sacrificial layers, recessing the fin-shaped structure to form a source/drain recess, recessing the sidewalls of the sacrificial layers to form inner spacer recesses, depositing a dielectric layer over the substrate and the inner spacer recesses, depositing a polymer layer over the dielectric layer, etching back the polymer layer and the dielectric layer to form inner spacer features in the inner spacer recesses and an inner spacer layer over the portion of the substrate, and epitaxially depositing more than one epitaxial layer from the sidewalls of the plurality of channel layers to form a source/drain feature in the source/drain recess. The source/drain feature and the inner spacer layer define a gap.