Multigate Source/Drain Void Structure for Bottom Leakage Reduction
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Solution Overview
Problem
As gate-all-around (GAA) devices continue to scale, the addition of multiple stacked channel layers degrades their performance, posing challenges in maintaining gate control and mitigating short-channel effects while integrating with conventional IC manufacturing processes.
Innovation Solution
A method for fabricating a multigate device that includes forming a void in the source/drain region between the source/drain feature and the bottom surface, using a specific fabrication process that involves forming semiconductor layer stacks, recessing the source/drain regions, depositing a spacer layer, and etching to form inner spacers and a void, ultimately leading to the growth of epitaxial source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stacked channel layers are added to GAA devices, then gate control is improved and short-channel effects are reduced, but device performance degrades due to increased complexity
Solution Approach 1:
The source/drain region is segmented into multiple discrete components: inner spacers, void regions, and epitaxial source/drain features. This segmentation allows independent optimization of each component's function, managing the complexity introduced by multiple stacked channel layers while maintaining effective gate control.
Solution Approach 2:
Different regions of the source/drain structure are assigned different properties: the inner spacers provide mechanical support and define boundaries, the void regions reduce bottom leakage locally, and the epitaxial features provide conductive pathways. This local differentiation addresses performance degradation in specific areas without requiring complete redesign of the entire device.
2Reliability
If source/drain regions are recessed to form voids, then bottom leakage is reduced and performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The inner spacers are formed in advance before the epitaxial source/drain features are grown. This preliminary action pre-defines the void regions and structural boundaries, enabling subsequent epitaxial growth to proceed in a controlled manner while achieving bottom leakage reduction without requiring complex post-processing steps.
Solution Approach 2:
The inner spacers act as intermediary structures that mediate between the recessed source/drain regions and the final epitaxial features. They provide a template and structural support during fabrication, simplifying the overall process by breaking down the complex void formation into manageable sequential steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances the performance of GAA devices by reducing bottom leakage and improving Ion and Ioff performance, while also reducing the area of the N well pickup for PMOS transistors and the P well pickup for NMOS transistors.
Implementation Method 1
performing a deposition process to form an inner spacer layer in the source/drain recess. The inner spacer layer is disposed on the semiconductor layer stack and the mesa structure of the substrate
Implementation Method 2
performing a deposition process to form an inner spacer layer in the source/drain recess
Implementation Method 3
epitaxially growing a source/drain feature from the semiconductor layer stack such that the source/drain feature fills the source/drain recess and a void is formed between the inner spacer and the source/drain feature
Data Source
AI summary
Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.