Multi-Gate Transistor Inner Spacer Layout for Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices scale down, there is a need to improve device performance and reliability by reducing parasitic capacitance and enhancing current control capabilities while minimizing the short channel effect.
Innovation Solution
The semiconductor device incorporates a multi-gate transistor structure with first and second active patterns, each featuring inner gates, source/drain patterns, and nitrogen build-up areas within inner spacers, which enhance electrical stability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch size of semiconductor devices is decreased to increase density, then device density is improved, but parasitic capacitance increases which degrades electrical stability
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional multi-gate structures (FinFET, nanowire, or cage-like configurations) that wrap around the active channel in vertical and lateral dimensions. This dimensional change allows for better gate control over the channel while maintaining reduced parasitic capacitance through optimized spacing between gate structures, thus resolving the contradiction between increased density and maintained electrical stability.
Solution Approach 2:
The gate structure is segmented into multiple independent gates (first inner gates, second inner gates, outer gates) that can be independently controlled and positioned. This segmentation allows for optimized spacing between gate elements to minimize parasitic capacitance while maintaining high density through multi-channel active patterns arranged in three-dimensional configurations.
2Ease of manufacture
If conventional planar transistors are used, then manufacturing is simpler, but current control capabilities are insufficient and short channel effect cannot be suppressed
Solution Approach 1:
The patent employs three-dimensional active patterns including fins, nanowires, or cage-like structures where gates wrap around channels in multiple dimensions. This multi-gate configuration provides superior electrostatic control over the channel, effectively suppressing short channel effects and enhancing current control capabilities while remaining compatible with standard semiconductor manufacturing processes through sequential formation steps.
3Reliability
If gate length is increased to improve current control, then current control capability is improved, but device density decreases
Solution Approach 1:
Instead of increasing gate length in the lateral direction, the patent utilizes vertical and three-dimensional gate configurations where gates wrap around channels. This approach improves current control through enhanced electrostatic control from multiple gate surfaces contacting the channel, while maintaining compact lateral footprints that preserve high device density through multi-channel parallel operation.
Data Source
AI summary
A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adjacent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.