Multigate Stepwise Isolation Structure for GAA Scaling
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in fabrication that degrade performance and increase processing complexity, limiting their effectiveness in advanced IC manufacturing.
Innovation Solution
A method for fabricating multigate devices, including GAA transistors, with stepwise isolation features and optimized source/drain profiles, utilizing epitaxial growth and selective etching to enhance gate control and reduce parasitic capacitance and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA device fabrication methods are used, then gate structure can be formed, but manufacturing complexity increases and device performance degrades
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (first patterning process and second patterning process) with each step creating specific trench structures. This segmentation allows complex isolation features to be built through manageable sequential steps rather than attempting to create the entire structure in one step, thereby reducing manufacturing complexity while achieving high device performance
Solution Approach 2:
The patent introduces stepwise isolation features with varying depths (first depth, second depth, third depth) to create three-dimensional isolation structures. This dimensional approach allows the gate structure to be isolated at multiple levels, improving gate control and reducing short-channel effects without requiring excessively complex planar processing
2Productivity
If IC dimensions are reduced to improve production efficiency, then production efficiency increases, but manufacturing process complexity increases
Solution Approach 1:
Isolation features are formed prior to gate structure fabrication through preliminary patterning processes. This preliminary action prepares the substrate with appropriate isolation structures before the main gate fabrication sequence, enabling efficient scaling to smaller dimensions without compounding process complexity
Solution Approach 2:
The patent applies different isolation depths and structures to different regions of the device (first circuit region, second circuit region, third circuit region). This local differentiation allows optimization for specific performance requirements in different areas while maintaining overall manufacturing efficiency through a unified process framework
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves GAA device performance by optimizing gate-channel coupling and reducing short-channel effects, facilitating faster switching and higher packing density while maintaining manufacturing efficiency.
Implementation Method 1
forming a semiconductor stack on the substrate, wherein the semiconductor stack includes first semiconductor layers of a first composition and second semiconductor layers of a second composition alternatively stacked on the substrate
Implementation Method 2
performing a first patterning process to the semiconductor stack and the substrate to form first trenches having a first depth; and performing a second patterning process to the semiconductor stack and the substrate, thereby forming second trenches of a second depth in the first circuit region and third trenches of a third depth in the second circuit region
Data Source
AI summary
The present disclosure provides a method that includes providing a substrate including a first circuit region and a second circuit region; forming a semiconductor stack on the substrate, wherein the semiconductor stack includes first semiconductor layers of a first composition and second semiconductor layers of a second composition alternatively stacked on the substrate; performing a first patterning process to the semiconductor stack and the substrate to form first trenches having a first depth; and performing a second patterning process to the semiconductor stack and the substrate, thereby forming second trenches of a second depth in the first circuit region and third trenches of a third depth in the second circuit region, the third depth being less than the second depth.