Multi-Gate STI Transistor Structure for CIS Noise Reduction
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Solution Overview
Problem
As CMOS image sensors (CIS) are scaled down for higher resolution, they face increased random telegraph signal (RTS) noise and dark current leakage due to transistor scaling, which is exacerbated by the limited space in shallow trench isolation (STI) structures, making it difficult to further miniaturize planar gate transistors and multi-gate transistors are still susceptible to noise.
Innovation Solution
A multi-gate transistor is implemented within an STI structure with a first doped liner on inner sidewalls and a thicker second doped liner on outer sidewalls, optimizing the channel region width to reduce noise while maintaining effective operation, and the transistor is formed with a single etch to minimize substrate damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down for higher resolution CIS, then device density and resolution are improved, but random telegraph signal noise and dark current leakage increase
Solution Approach 1:
The patent applies local quality by implementing asymmetric doped liners with different thicknesses at different locations within the STI structure. A first doped liner is formed on the inner sidewall facing the channel region with a specific thickness, while a second doped liner is formed on the outer sidewall with a different thickness. This localized differentiation allows optimization of noise suppression and current leakage prevention in specific regions without affecting the entire device uniformly, thereby reducing harmful effects while maintaining high device density.
2Productivity
If planar gate transistors are miniaturized, then device density is improved, but available space in STI structure is reduced making further miniaturization difficult
Solution Approach 1:
The patent transitions from conventional planar gate transistors to multi-gate transistors with inverted U-shaped, omega-shaped, or other-shaped cross-sectional profiles that partially laterally surround the sidewalls of the channel region. This dimensional change allows the gate electrode to extend into the vertical and lateral dimensions within the STI structure, effectively utilizing the available space more efficiently and enabling further miniaturization without compromising device performance.
3Productivity
If multi-gate transistors are used to overcome miniaturization limits, then device density is improved, but susceptibility to noise remains
Solution Approach 1:
The patent employs composite material structures by combining the multi-gate transistor architecture with doped liner materials within the STI structure. The doped liners are integrated with the multi-gate structure, creating a composite system where the doped regions provide noise suppression benefits while the multi-gate configuration maintains high device density. This composite approach allows simultaneous achievement of miniaturization and noise reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces noise and minimizes current leakage, enabling effective channel region induction during CIS operation while allowing for further scaling of transistors in high-resolution CIS applications.
Implementation Method 1
A dopant is implanted into the STI trench forming a first doped liner on an inner portion of the STI trench
Data Source
AI summary
The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.