Multi-Gate Semiconductor Fabrication With STI-Protective Dielectric Layer
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining performance and reducing manufacturing defects, particularly in the formation of multi-gate devices like FinFETs and GAA devices.
Innovation Solution
A method for fabricating multi-gate devices involves forming epitaxial stacks with sacrificial layers and channel layers, patterning fins, depositing dielectric layers, and replacing sacrificial gates with high-K metal gates, utilizing precise etching and deposition techniques to ensure precise feature formation and minimize defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but manufacturing defects increase and process control becomes more difficult
Solution Approach 1:
The patent segments the gate formation process into multiple distinct stages: forming sacrificial gates, depositing first spacers, forming second spacers, and selective removal. This segmentation allows each step to be optimized independently, maintaining precision even as feature sizes decrease to improve integration density.
Solution Approach 2:
The patent employs preliminary actions by first forming sacrificial gates and spacers before creating the final gate structure. These preliminary structures guide subsequent processing steps and ensure precise feature formation. The sacrificial gates are formed at predetermined locations before the actual gate structures, enabling controlled material deposition and pattern transfer at reduced feature sizes.
2Reliability
If multi-gate devices are formed to improve performance, then device functionality is enhanced, but process complexity increases
Solution Approach 1:
The patent employs universal spacer deposition processes that can be applied across different device regions. The same spacer material and deposition technique are used for both the first and second spacers, as well as for gate spacers and mandrel spacers. This multi-functionality reduces process complexity while still enabling sophisticated multi-gate device formation with enhanced performance.
Solution Approach 2:
The patent uses sacrificial gates and spacers as intermediary structures that facilitate the formation of complex multi-gate devices. These intermediary elements are temporarily formed to guide material deposition and define feature locations, then selectively removed to create the final device structure. This intermediary approach simplifies the overall process by breaking down complex formation steps into manageable sequences.
3Manufacturing precision
If precise etching and deposition techniques are used to minimize defects, then manufacturing quality improves, but production time increases
Solution Approach 1:
The patent employs continuous deposition processes where spacer materials are deposited conformally over previously formed structures without breaking the process flow. The first spacers are deposited continuously over sacrificial gates, then second spacers are deposited continuously over the first spacers. This continuity maintains manufacturing precision while improving productivity by eliminating interruptions and repositioning steps.
Solution Approach 2:
The spacer deposition process is self-aligning and self-defining, requiring minimal additional patterning steps. The conformal deposition automatically creates uniformly thick spacers that self-align to the underlying sacrificial structures. This self-service characteristic maintains high manufacturing precision while reducing the number of separate processing steps, thereby improving fabrication speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances integration density and reduces manufacturing defects, improving the performance and reliability of multi-gate devices by optimizing the formation of gate structures and channel regions.
Implementation Method 1
depositing a dielectric layer above shallow trench isolation (STI) features
Data Source
AI summary
A semiconductor fabrication method includes: depositing a dielectric layer above shallow trench isolation (STI) features formed between a first fin and a second fin on a substrate that each include an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer, wherein dielectric layer reduces STI loss during subsequent etching operations; patterning a sacrificial gate stack on channel regions of the first fin; forming gate spacers, performing source/drain (S/D) etching operations on opposite sides of the sacrificial gate stack and forming inner gate spacers; forming an S/D region; forming a contact etch stop layer (CESL); and replacing the sacrificial gate stack with a metal gate.