Multi-gate Thin-Film Transistor for Compact Display Charge Control
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Solution Overview
Problem
Conventional synchronous frame update schemes in display elements, such as IMOD and LCDs, require many capacitors and transistors, making them difficult to implement in compact forms while ensuring reliability, especially when both compactness and reliability are design concerns.
Innovation Solution
The implementation of multi-gate thin-film transistors, specifically three-gate thin-film transistors, which include a storage gate electrode that switches between high and low capacitance states to efficiently store and transfer charge, reducing the need for multiple capacitors and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional synchronous frame update schemes use many capacitors and transistors to ensure reliable charge storage and transfer, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent combines multiple functions (charge storage, charge transfer control, and capacitance switching) into a single multi-gate TFT structure. The first gate electrode provides charge transfer control, the second gate electrode provides capacitance switching between high and low states, and the third gate electrode provides additional charge transfer control, eliminating the need for separate capacitors and transistors
Solution Approach 2:
The multi-gate TFT serves multiple functions simultaneously: it acts as a charge storage element, a charge transfer switch, and a capacitance switch. The ability to switch between high and low capacitance states while controlling charge transfer makes the device universal, replacing what would traditionally require multiple separate components
2Reliability
If conventional schemes use many capacitors and transistors to ensure reliable operation, then reliability is improved, but the compact form factor is compromised
Solution Approach 1:
The patent integrates charge storage, charge transfer control, and capacitance switching functions into a single compact multi-gate TFT structure, eliminating the need for multiple separate capacitors and transistors that would occupy additional area in the display device
Solution Approach 2:
The patent utilizes vertical stacking of gate electrodes above and below the semiconducting layer to achieve multiple functions within a compact planar footprint, effectively using the third dimension to reduce the area required on the display surface
3Device complexity
If the transistor structure is simplified to reduce device complexity, then ease of manufacture is improved, but charge transfer control precision deteriorates
Solution Approach 1:
The patent segments the gate control function into multiple independent gate electrodes, each controlling different aspects of charge transfer. The first gate electrode controls charge transfer from drain to source, the second gate electrode controls capacitance state, and the third gate electrode provides additional transfer control, allowing precise independent control of each function
Solution Approach 2:
The patent implements dynamic capacitance switching by applying different voltages to the second gate electrode, allowing the device to switch between high and low capacitance states during operation. This dynamic control enables precise timing and control of charge transfer operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient charge injection and transfer to display elements, reducing power consumption and allowing for accurate charge control despite varying capacitance states, thereby improving the reliability and compactness of display systems.
Implementation Method 1
a storage gate electrode that switches between high and low capacitance states to efficiently store and transfer charge
Implementation Method 2
charge is transferred in from the drain and accumulated in a potential well in a region of the semiconducting layer adjacent to the second gate electrode
Data Source
AI summary
This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.