Multi-Gate Transistor Fabrication via Isolation Layer Etching

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Solution Overview

Problem

The reduction in gate length of semiconductor devices leads to performance degradation in traditional planar single-gate transistors, and the formation of multi-gate transistors with three-dimensional active patterns is challenging due to misalignment issues during isolation layer removal, which can result in undesired channels and reduced reliability.

Innovation Solution

A method of fabricating semiconductor devices involves forming grooves between active patterns, burying them with passivation layers, and selectively etching to expose both sides of the active patterns, allowing for the formation of gate lines that improve channel formation and device reliability, even with partial misalignment of mask patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the isolation layer between active patterns is removed to form three-dimensional active patterns for multi-gate transistors, then the current capability is improved by more than three times, but misalignment of mask patterns causes active patterns to separate and undesired channels to form, reducing reliability

Engineering Contradiction:

Improvecurrent capabilityVSAvoiddevice reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A protective layer is formed over the active patterns before removing the isolation layer. This preliminary protective action prevents misalignment issues from causing active pattern separation and undesired channel formation, allowing the isolation layer to be safely removed to achieve the multi-gate transistor current enhancement without reliability penalties

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective layer acts as an intermediary element between the isolation layer and the active patterns. It enables the removal of the isolation layer to create three-dimensional active patterns while preventing direct exposure and potential misalignment damage to the active patterns themselves, thus maintaining reliability while achieving improved current capability

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If mask patterns are misaligned during isolation layer removal, then the fabrication process becomes simpler, but active patterns separate and undesired channels form, reducing device reliability

Engineering Contradiction:

Improvefabrication process simplicityVSAvoiddevice reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The protective layer is deposited beforehand to cushion and protect the active patterns during the isolation layer removal process. This prior cushioning ensures that even if mask alignment is not perfect, the active patterns remain protected from separation and undesired channel formation, maintaining reliability while allowing for easier manufacturing with relaxed alignment tolerances

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Ease of manufacture

If traditional planar single-gate transistor structure is used, then the fabrication process is simpler, but performance degradation occurs due to reduction of gate length

Engineering Contradiction:

Improvefabrication process simplicityVSAvoiddevice performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The method transitions from a traditional planar single-gate structure to a three-dimensional multi-gate structure by removing the isolation layer and forming gates that wrap around the active patterns. This dimensional change enables improved performance with reduced gate length while the protective layer ensures the process remains manageable and reliable

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the reliability and performance of semiconductor devices by ensuring complete separation of active patterns and preventing undesired channel formation, thereby improving the integration and performance of multi-gate transistors.

Implementation Method 1

forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

burying the first groove with a passivation layer

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS7846801B2Method of fabricating semiconductor device

Publication Date: 2010.12.07 SAMSUNG ELECTRONICS CO LTD

AI summary

Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.