Multi-Gate Transistor Selective Epitaxial Growth
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Solution Overview
Problem
Conventional FinFET manufacturing processes damage the lattice of the fin film due to ion implantation, and high-temperature anneal treatments deteriorate the stability of the high-K insulating layer, limiting the thermal budget and device performance.
Innovation Solution
The method involves replacing ion implantation and anneal treatment with selective epitaxial growth (SEG) to form an epitaxial layer on the surface of a patterned semiconductor layer, which serves as the raised source/drain, thereby avoiding lattice damage and adverse effects on the gate dielectric layer, and providing strain stress to improve channel region mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation and high-temperature anneal treatment are used to form source/drain, then the source/drain can be formed with proper doping, but the lattice of the fin film is damaged and the stability of the high-K insulating layer deteriorates
Solution Approach 1:
The patent changes the fundamental process parameters from ion implantation (high energy, damaging) to selective epitaxial growth (low energy, non-damaging). The epitaxial growth process occurs at lower temperatures and uses chemical vapor deposition to grow silicon layers with proper doping, eliminating lattice damage while maintaining source/drain formation quality.
Solution Approach 2:
The patent replaces the mechanical ion implantation process with a chemical epitaxial growth process. Instead of physically bombarding the substrate with ions, the method uses chemical vapor deposition to grow doped silicon layers epitaxially on the semiconductor surface, achieving doping without mechanical damage.
2Manufacturing precision
If high-temperature anneal treatment is performed to repair ion implantation damage, then lattice damage can be repaired, but the stability of the high-K insulating layer deteriorates
Solution Approach 1:
The patent converts the harmful high-temperature annealing process into a beneficial low-temperature epitaxial growth process. The epitaxial growth naturally repairs any potential damage during the growth process itself at lower temperatures, eliminating the need for separate high-temperature repair steps that would damage the gate dielectric.
Solution Approach 2:
The patent performs the doping and lattice formation action during the epitaxial growth process itself, before any potential damage can occur. The doped silicon layers are grown with proper crystal structure and doping concentration in a single controlled process, preventing the need for subsequent high-temperature repair annealing.
3Quantity of substance
If conventional ion implantation is used to form source/drain, then doping can be achieved, but lattice damage occurs that limits device performance
Solution Approach 1:
The patent replaces mechanical ion implantation with chemical epitaxial growth for doping. The epitaxial growth process incorporates dopants chemically during the silicon layer formation, achieving precise doping concentrations without the mechanical damage inherent in ion implantation.
Solution Approach 2:
The patent changes the doping mechanism from physical ion implantation to chemical incorporation during epitaxial growth. This allows precise control of doping concentration through gas flow ratios and process parameters while maintaining perfect crystal lattice structure throughout the doped region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and device performance by eliminating lattice damage and stability issues, while integrating effectively with high-K gate dielectric materials and metal gate processes.
Implementation Method 1
performing a selective epitaxial growth (SEG) process to form an epitaxial layer on a surface of the second patterned semiconductor layer
Implementation Method 2
by forming the epitaxial layer on the surface of the second patterned semiconductor layer, strain stress is provided to the channel region of the multi-gate transistor device more effectively. Accordingly, the mobility in the channel region is improved
Data Source
AI summary
A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.