Multi-Gate Transistor Formation With Selective Sacrificial Deposition

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Solution Overview

Problem

The formation of extraneous oxide layers on semiconductor substrates during the manufacturing of nano-FETs can impact subsequent process steps and device performance, particularly when forming sacrificial materials in the gate-last process.

Innovation Solution

A nitrogen-containing plasma treatment is applied to the exposed surfaces of fins and nanostructures to make them less susceptible to the deposition of a sacrificial material layer, followed by a conformal deposition and selective etching to minimize the presence of sacrificial material on these surfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a sacrificial material layer is deposited conformally on channel regions and fins, then the gaps between channel regions are filled to form sacrificial material structures, but extraneous oxide layers form on the exposed surfaces of fins and nanostructures impacting device performance

Engineering Contradiction:
Improveformation of sacrificial material structuresVSAvoidextraneous oxide layer formation
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

A surface treatment is applied to the exposed surfaces of fins and nanostructures before depositing the sacrificial material layer. This preliminary treatment modifies the surface properties to reduce the susceptibility of these surfaces to oxide layer formation during subsequent processing steps, thereby preventing the harmful effect before it occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The surface treatment is applied selectively only to the exposed surfaces of fins and nanostructures that are adjacent to channel regions, while leaving other surfaces untreated. This creates local differentiation in surface properties, ensuring that oxide layer formation is suppressed only where it would be harmful, while maintaining normal oxidation behavior elsewhere.

Inventive Principle:
Principle #3Local quality

2Productivity

If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but additional manufacturing problems arise including increased susceptibility to oxide layer formation

Engineering Contradiction:
Improveintegration densityVSAvoidoxide layer formation impact
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The surface treatment modifies the physical or chemical parameters of the fin and nanostructure surfaces, changing their reactivity toward oxidation. This parameter change allows the structures to maintain their small dimensions for high integration density while simultaneously reducing their susceptibility to harmful oxide layer formation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing defects and improves device performance by minimizing the impact of sacrificial material on critical dimensions and electrical properties of nano-FETs.

Implementation Method 1

A nitrogen-containing plasma treatment is applied to the exposed surfaces of fins and nanostructures to make them less susceptible to the deposition of a sacrificial material layer

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Implementation Method 2

a conformal deposition and selective etching to minimize the presence of sacrificial material on these surfaces

Methodology Applied
Scientific EffectConformal deposition: Chemical Vapour Deposition

Data Source

PatentUS20260052957A1Method of forming multi-gate transistors and resulting structures
Publication Date: 2026.02.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260052957A1 patent drawing
  • US20260052957A1 patent drawing
  • US20260052957A1 patent drawing

AI summary

Forming a semiconductor device includes forming over a surface of a fin a stack of channel regions separated by respective gaps and applying a surface treatment to sidewalls of the channel regions and to the surface of the fin thus causing the sidewalls of the channel regions and the surface of the fin to be less susceptible to deposition of a sacrificial material layer, relative to prior to the surface treatment, and depositing the sacrificial material layer on the channel regions and on the surface of the fin, wherein the surface treatment causes deposition of the sacrificial material to occur to a lesser extent on the sidewalls of the channel regions and the surface of the fin relative to the tops and bottoms of the channel regions, and etching back the sacrificial material layer to form sacrificial material structures within the respective gaps.