Multi-Gate Transistor Strain Engineering via Selective Epitaxy
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Solution Overview
Problem
Multi-gate devices face limitations in reducing parasitic resistance and enhancing channel mobility due to challenges in controlling dopant concentration and location in fin regions, as well as the inability to adapt strain-inducing mobility enhancement techniques from planar devices.
Innovation Solution
The method involves forming epitaxial source and drain extensions with a vertical thickness equal to the fin height, using ion implantation to create doped regions that are selectively etched to form regrown source and drain regions under the gate dielectric, and filling these regions with a material that induces strain on the channel, optimizing the etch profile and stress for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopant implantation and diffusion method is used to reduce parasitic resistance, then resistance is reduced, but control over dopant concentration and location is limited
Solution Approach 1:
The patent changes the fundamental parameter of dopant introduction from post-growth implantation/diffusion to in-situ doping during selective epitaxial growth. This allows precise control of dopant concentration and location by controlling growth conditions rather than relying on thermal diffusion processes, directly resolving the contradiction between resistance reduction and manufacturing precision
Solution Approach 2:
The patent performs preliminary patterning of the fin structure to define precise locations where dopant-containing semiconductor material will be selectively grown. By pre-defining the geometry and location of source/drain regions through etching and masking before epitaxial growth, the process achieves high manufacturing precision in dopant placement while maintaining low resistance
2Reliability
If strain-inducing mobility enhancement techniques are applied to planar devices, then channel mobility is enhanced, but these techniques cannot be readily adapted to multi-gate devices
Solution Approach 1:
The patent employs composite semiconductor materials with different lattice constants (e.g., SiGe source/drain regions with silicon channel) to induce strain in the channel. The lattice mismatch between the composite source/drain material and the channel creates mechanical strain that enhances carrier mobility, successfully adapting strain-inducing techniques to multi-gate FinFET structures through material composition rather than geometric deformation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overall resistance and increases channel strain, allowing for better control of dopant concentration and location, thereby enhancing the operational performance of multi-gate devices by increasing drive current and mobility.
Implementation Method 1
ion implantation to create doped regions
Implementation Method 2
The doped fin regions are selectively etched to form cavities
Implementation Method 3
forming epitaxial source and drain extensions
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.