Multi-Gate Vertical FET Cell Architecture for Pin Accessibility
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Solution Overview
Problem
Conventional planar or horizontal field effect transistors have a gear ratio of 1:1, which limits the improvement of pin accessibility, routability, and cell density, and require an additional vertical metal routing layer, increasing manufacturing complexity and cost.
Innovation Solution
A cell architecture based on multi-gate vertical field effect transistors (VFETs) with two or more fins, where the gate and source/drain structures serve as conductive routing layers, eliminating the need for an additional metal routing layer by using metal patterns connected through vias, achieving a gear ratio greater than 1:1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional planar or horizontal field effect transistors are used, then the gear ratio is 1:1, but pin accessibility, routability, and cell density are limited
Solution Approach 1:
The patent transitions from conventional planar or horizontal FET architectures to a vertical FET architecture where the channel extends in the vertical dimension. This dimensional change enables the gate to wrap around the vertical channel, creating multiple gate contacts that can be accessed from different directions, thereby improving pin accessibility and enabling higher gear ratios without requiring additional metal routing layers.
2Adaptability or versatility
If conventional planar or horizontal field effect transistors are used, then the gear ratio is 1:1, but cell density is limited
Solution Approach 1:
By moving to a vertical FET architecture, the patent utilizes the vertical dimension to accommodate multiple gate contacts and source/drain regions. This allows for more compact cell layouts and higher cell density while achieving improved gear ratios, as the vertical structure reduces the horizontal footprint required for each transistor.
Solution Approach 2:
The vertical channel is segmented into multiple sections with gate contacts positioned at different heights and locations. This segmentation allows for multiple independent gate controls and improved routing flexibility, enabling higher gear ratios and better cell density without requiring additional metal layers.
3Adaptability or versatility
If an additional vertical metal routing layer is added to improve gear ratio, then pin accessibility and routability improve, but manufacturing complexity and production cost increase
Solution Approach 1:
The patent makes the gate structure multi-functional by using it both as the transistor gate and as a conductive routing element. The gate contacts and gate structure itself serve dual purposes: controlling the channel and providing electrical connections for routing signals. This eliminates the need for separate vertical metal routing layers, reducing manufacturing complexity while maintaining improved gear ratios.
Solution Approach 2:
The patent merges the gate function with the routing function by using the gate structure and its contacts as both control elements and conductive pathways. This consolidation eliminates the need for additional dedicated routing layers, simplifying the manufacturing process and reducing production costs while achieving the desired gear ratio improvements.
Data Source
AI summary
A cell architecture is provided. A cell architecture including a vertical field effect transistor (VFET) having at least two fins serving as a vertical channel, a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing connection therebetween, and a top source/drain (S/D) including a first top S/D portion on the first fin and a second top S/D portion on the second fin, a gate contact structure connected to the third gate portion, a top S/D contact structure connected to one of the first top S/D portion or the second top S/D portion and serving as a horizontal conductive routing layer; and metal patterns on the gate contact structure and the top S/D contact structure and connected thereto through vias, and serving as a vertical conductive routing layer may be provided.