Multi-Hop Clock Synchronization via Intermediate Node Timing
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Solution Overview
Problem
Current clock synchronization methods in multi-hop wireless relay networks suffer from reduced precision due to hop-by-hop synchronization errors, especially in 5G new radio systems, where stricter synchronization requirements are needed to prevent uplink-downlink interference and improve system performance.
Innovation Solution
A communication processing method where intermediate nodes add waiting time information to messages between target and synchronization source nodes, allowing the target node to calculate clock deviations based on sending and receiving times, and transmission delays, enabling precise clock adjustment and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hop-by-hop synchronization method is used in multi-hop wireless relay network, then synchronization can be implemented between nodes, but synchronization precision deteriorates significantly with increasing hop count
Solution Approach 1:
The patent introduces an intermediary mechanism where intermediate nodes do not perform independent synchronization decisions but instead transparently forward timing information from the synchronization source to the target node. The target node directly calculates clock deviation using timing data from the source, bypassing the need for each node to independently synchronize with its neighbor, thus maintaining precision across multiple hops
Solution Approach 2:
The patent segments the synchronization process into two distinct phases: (1) timing information collection and forwarding by intermediate nodes, and (2) clock deviation calculation and correction at the target node. This segmentation allows intermediate nodes to remain transparent while the target node performs precise synchronization based on direct timing measurements from the source
2Device complexity
If cross-hop synchronization solution is used where target node performs clock synchronization directly with synchronization source node, then hop count limitation is removed, but synchronization precision deteriorates due to assumption of equal forward and reverse path delays
Solution Approach 1:
The patent implements a feedback mechanism where the target node sends a first message to the synchronization source node, and the source node responds with a second message containing the actual receiving time of the first message. This feedback loop allows the target node to measure the actual round-trip delay and calculate one-way delay more accurately, compensating for path asymmetry without requiring equal forward and reverse delay assumptions
Solution Approach 2:
The patent performs preliminary timing measurements by having the target node send a probe message to the synchronization source before actual synchronization. The source node records the receiving time and sends it back, allowing the target node to pre-calculate the actual transmission delay and use this information for accurate clock synchronization, rather than assuming equal delays
Data Source
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AI summary
This application provides a communication processing method and apparatus. The method includes: receiving, by a target node, a second message sent by a synchronization source node via at least one intermediate node, where the second message carries a receiving time of a first message from the target node at the synchronization source node and waiting time information of the first message at each of the at least one intermediate node; and determining, by the target node, a clock deviation between the target node and the synchronization source node based on a sending time of the first message at the target node and the second message. According to the communication processing method and apparatus in embodiments of this application, clock synchronization can be implemented in a multi-hop relay scenario.