Multilane Clock Data Recovery Using Shared Phase-Error Aggregation
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, existing Clock Data Recovery (CDR) methods face challenges in maintaining accurate sampling timing due to varying signal propagation conditions and noise, especially in environments with multiple data lanes where rapid perturbations and independent channel variations are common, leading to increased power consumption and inefficiency.
Innovation Solution
The implementation of a data-driven phase error correction mechanism using decision feedback equalization and phase interpolation, which generates data-derived phase-error signals to adjust sampling clocks dynamically, ensuring accurate data capture across multiple data lanes while minimizing power consumption by sharing phase-lock loop components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If independent CDR circuits are used for each data lane, then sampling timing accuracy is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent combines multiple CDR circuits into a single shared CDR circuit that serves all data lanes. The shared circuit receives data from multiple lanes and generates a common recovered clock signal, eliminating the need for separate CDR circuits per lane. This merging approach maintains sampling timing accuracy through data-driven phase error correction while significantly reducing power consumption and device complexity.
Solution Approach 2:
The recovered clock circuit is designed to perform multiple functions: it processes data from multiple different data lanes simultaneously and generates sampling clocks for all lanes. The circuit universally handles phase error detection and correction across all input channels, making a single circuit serve the role of what would traditionally require multiple dedicated circuits.
2Measurement precision
If independent CDR circuits are used for each data lane, then sampling timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple independent CDR circuits into one unified recovered clock circuit that handles all data lanes. This consolidation reduces the number of separate components, simplifies the overall device architecture, and lowers device complexity while maintaining the necessary sampling timing accuracy through its data-driven phase correction mechanism.
3Reliability
If traditional CDR methods are used, then clock recovery is achieved, but noise resilience decreases in high-speed multilane environments
Solution Approach 1:
The patent implements a data-driven feedback mechanism where the recovered clock circuit continuously monitors incoming data for phase errors and dynamically adjusts its output clock signal accordingly. This feedback loop detects phase deviations caused by noise and propagation variations in real-time and corrects them, significantly improving noise resilience while maintaining reliable clock recovery in high-speed multilane environments.
Data Source
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AI summary
Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (i) a phase of one or more phases of a local oscillator signal and (ii) a corresponding data signal associated with one of the two or more data lanes, generating a composite phase-error signal representing a combination of the two or more obtained data-derived phase-error signals, receiving the composite phase-error signal at a loop filter responsively generating an oscillator control signal, and receiving the oscillator control signal at a local oscillator and responsively adjusting a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.