Multilane Clock Recovery Using Aggregated Phase-Error Signals
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, existing Clock and Data Recovery (CDR) methods face challenges in maintaining accurate phase synchronization and power efficiency, especially in environments with varying propagation conditions and noise, leading to increased power consumption due to the need for multiple Phase-Locked Loops (PLLs) for each data lane.
Innovation Solution
The system employs a phase-error aggregator to generate a composite phase-error signal from multiple data lanes, using local oscillator phases and data signals, which is then filtered to produce an oscillator control signal, allowing for adjustments to the local oscillator timing and reducing the need for multiple PLLs by using data-derived phase-error signals and decision feedback equalization to optimize sampling timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple Phase-Locked Loops (PLLs) are used for each data lane to maintain accurate phase synchronization, then phase synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple phase-error signals from different data lanes into a single composite phase-error signal. Instead of maintaining separate PLLs for each data lane, the system aggregates phase errors from multiple lanes and uses a single PLL to generate a common clock signal that serves all lanes, thereby reducing power consumption while maintaining synchronization accuracy.
Solution Approach 2:
The invention makes a single PLL serve multiple data lanes simultaneously. The clock recovery circuit generates a universal clock signal that is distributed to all data lanes, eliminating the need for lane-specific PLLs. This multi-functional approach reduces the total number of PLL circuits and their associated power consumption while maintaining accurate phase synchronization across all lanes.
2Reliability
If multiple PLLs are deployed for each data lane to handle varying propagation conditions and noise, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the clock recovery functionality across multiple data lanes by combining their phase-error signals into a single composite signal. This consolidation reduces the number of PLL circuits from one per lane to a single shared PLL, simplifying the overall system architecture while maintaining the ability to handle varying propagation conditions and noise through the aggregated phase-error information.
3Use of energy by moving object
If data-derived phase-error signals are used to optimize sampling timing, then power efficiency is improved, but measurement precision requirements increase
Solution Approach 1:
The system uses data-derived phase-error signals as feedback to continuously adjust the clock phase and optimize sampling timing. The phase-error aggregator combines feedback from multiple data lanes, and the PLL uses this aggregated feedback to dynamically adjust the clock signal, achieving power efficiency through optimized sampling while maintaining precision through continuous feedback adjustment.
Data Source
AI summary
Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (i) a phase of one or more phases of a local oscillator signal and (ii) a corresponding data signal associated with one of the two or more data lanes, generating a composite phase-error signal representing a combination of the two or more obtained data-derived phase-error signals, receiving the composite phase-error signal at a loop filter responsively generating an oscillator control signal, and receiving the oscillator control signal at a local oscillator and responsively adjusting a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.