Multilane Clock Recovery with Shared Master-Slave CDR Architecture
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Solution Overview
Problem
Conventional clock data recovery devices, especially combined CDR devices, suffer from duplicate circuits leading to increased circuit area and cost, which is unfavorable for miniaturization and cost-saving, particularly in multilane applications.
Innovation Solution
A clock data recovery device with a master circuit and multiple slave lane circuits, featuring a clock multiplication unit, sampling circuits, phase detectors, multiplexers, and loop filters, allowing operation in multiple modes through adaptive multiplexer settings to reduce redundant components and optimize circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a combined CDR device includes both analog CDR components (CP, LPF, VCO) and digital CDR components (CMU with charge pump, low pass filter, voltage-controlled oscillator), then the device can function in multiple modes (analog or digital), but the circuit area increases and cost increases due to duplicate circuits
Solution Approach 1:
The patent merges the charge pump, low pass filter, and voltage-controlled oscillator circuits into a shared resource that serves both the analog CDR path and digital CDR path. The master lane circuit contains one set of these components that can be selectively connected to serve either the analog phase detector or the digital phase frequency detector, eliminating the need for duplicate circuits in each path.
Solution Approach 2:
The clock multiplication unit and its associated components (charge pump, LPF, VCO) are designed with multi-functionality to serve dual purposes: they can operate as part of the digital CDR system when the CMU is enabled, or as part of the analog CDR system when the CMU is disabled and the analog PD is used. This universal design allows one set of components to replace what would traditionally require separate dedicated circuits for each mode.
2Adaptability or versatility
If each lane in a multilane application uses a combined CDR device with duplicate circuits, then each lane can independently function in multiple modes, but the overall circuit area becomes very large
Solution Approach 1:
The patent segments the CDR functionality into lane-specific components (phase detectors, sampling circuits, multiplexers) that can be independently configured for each lane, while sharing the resource-intensive components (charge pump, LPF, VCO) at the master lane level. This segmentation allows each lane to maintain multi-mode capability through its own phase detector and multiplexer, while the shared resources reduce the overall area burden.
Solution Approach 2:
The patent implements a nested structure where the slave lane circuits are integrated with and dependent on the master lane circuit's clock multiplication unit. The slave lanes nest their phase detectors and sampling circuits within the overall system architecture that shares the master lane's VCO and filtering resources, creating a hierarchical structure that optimizes area usage while maintaining per-lane functionality.
3Adaptability or versatility
If a combined CDR device includes multiplexers to switch between analog and digital modes, then mode switching is enabled, but the device complexity increases
Solution Approach 1:
The patent implements dynamic reconfiguration capability where the multiplexers can switch between connecting the analog phase detector or digital phase frequency detector to the shared charge pump and VCO. This dynamic switching mechanism allows the system to adapt its configuration based on the required operating mode (analog CDR or digital CDR) without requiring physically separate circuits for each mode, thereby managing complexity through controlled reconfigurability rather than static duplication.
Data Source
AI summary
Disclosed is a clock data recovery (CDR) device including a master lane circuit and a plurality of slave lane circuits. The master lane circuit includes: a clock multiplication unit including a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), and a loop divider; a master lane sampling circuit; a master lane phase detector (PD); and a master lane multiplexer coupled between the master lane PD and the CP and between the PFD and the CP. Each slave lane circuit includes: a slave lane sampling circuit (SLS); a slave lane PD; a slave lane digital loop filter; a phase rotator (PR); and a slave lane multiplexer coupled between the VCO and the SLS and between the PR and the SLS, in which the master lane multiplexer and the slave lane multiplexers are configured to have the CDR device operate in one of multiple modes.