Multilane Clock Skew Correction Using DLL Edge Selection
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Solution Overview
Problem
Current semiconductor devices face challenges in accurately synchronizing data clock signals across multiple lanes, leading to communication channel skew issues that affect data recovery and communication rates.
Innovation Solution
A skew correcting device and method that utilize samplers and edge selectors to determine and adjust data clock signals, employing a delay-locked loop (DLL) circuit to generate edge clock signals for synchronizing start timings and correcting skew between lanes, thereby improving clock and data recovery (CDR) operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data clock signals are used for sampling across multiple lanes, then communication rate and data recovery capability are improved, but skew between lanes increases and synchronization becomes more difficult
Solution Approach 1:
The patent implements a feedback mechanism where sampling results from multiple lanes are fed back to the edge selector, which then adjusts the data clock signal selection based on detected edges. This closed-loop feedback enables dynamic synchronization adjustment, allowing the system to maintain accurate timing across multiple lanes while operating at high communication rates.
Solution Approach 2:
The edge selector acts as an intermediary component between the multiple data clock signals and the sampling circuits. It selectively switches between different data clock signals based on edge detection, mediating the timing differences between lanes and enabling synchronized operation without directly modifying the clock signal generation.
2Measurement precision
If edge detection and clock signal switching are implemented to correct skew, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the edge selector component: edge detection, clock signal selection, and switching control are integrated into a single circuit block. This merging reduces the overall system complexity by eliminating the need for separate control logic and multiple independent components, while still achieving accurate skew correction.
Solution Approach 2:
The edge selector is designed as a universal component that can handle multiple data clock signals from different lanes and selectively switch between them based on edge detection. This multi-functional design allows a single component to address synchronization issues across all lanes, reducing the need for lane-specific correction circuits.
Data Source
AI summary
The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.