Multi-Lane Data Reception System with Dynamic Skew Alignment
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Solution Overview
Problem
Conventional transmission and reception systems face challenges in performing cut-through transfers when skew variations occur between lanes, leading to communication latency issues, data destruction, and decreased transfer performance due to difficulties in timing estimation and error detection.
Innovation Solution
A system with error detection circuits, storage circuits, a selection circuit, and a report circuit is implemented to detect errors, store data, select optimal transmission paths, and report read timings and positions, allowing for dynamic alignment and error handling to maintain communication quality and reduce circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If cut-through transfer is performed without error detection and alignment, then communication latency is reduced, but data integrity deteriorates due to skew variations
Solution Approach 1:
The patent performs error detection and timing alignment in advance during the cut-through transfer process. The timing alignment circuit measures skew variations and adjusts read timings before data is fully transferred, while error detection circuits identify errors early. This preliminary action allows the system to maintain low latency by not waiting for complete data reception before detecting errors or adjusting timing.
Solution Approach 2:
The patent introduces intermediary circuits including timing alignment circuits that act as mediators between the skewed data streams from different lanes. These circuits measure timing differences and generate adjustment signals that coordinate the read operations across multiple lanes, enabling synchronized data reconstruction without requiring complete data reception first.
2Reliability
If multiple circuits are used for error detection and timing alignment, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into integrated circuits. The timing alignment circuit combines skew measurement, timing calculation, and control signal generation in a single unit. Similarly, error detection circuits are integrated with the data reception pathway, combining error checking with the existing data flow processing. This merging reduces the number of separate components while maintaining comprehensive error detection and timing alignment capabilities.
3Measurement precision
If data is stored and aligned before transfer, then timing accuracy is improved, but communication latency increases
Solution Approach 1:
The patent employs dynamic timing adjustment instead of static pre-alignment. The timing alignment circuit continuously measures skew variations and dynamically adjusts read timings during the transfer process. This dynamic approach allows the system to maintain high timing accuracy while avoiding the fixed delays associated with complete data storage and pre-alignment, thereby reducing communication latency.
Solution Approach 2:
The patent implements cut-through transfer that allows data to be read and forwarded before complete reception and alignment. By skipping the traditional wait-for-complete-data step and using real-time timing measurements to guide selective reading from storage circuits, the system achieves both timing accuracy and low latency by rushing through the transfer process with intelligent timing control.
Data Source
AI summary
A data reception apparatus connected to a data transmission apparatus via transmission paths includes: error detection circuits that are each provided for each of the transmission paths and that each detect an error in received data that has been received from the data transmission apparatus; storage circuits that are each provided for each of the transmission paths and that each store the received data and read the received data at a reported read position at a reported read timing; a selection circuit that selects one of the transmission paths according to error detection results provided by the error detection circuits; and a report circuit that compares received data stored by a storage circuit corresponding to a selected transmission path with received data stored by each of other storage circuits and, according to a comparison result, reports the read timing and the read position to each of the storage circuits.