Multi-Lane Decoding Circuit for Linear-Complexity CP-MLC
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Solution Overview
Problem
The operation amount of likelihood calculation in the decoding circuit of channel-polarized multilevel coding (CP-MLC) exponentially increases with respect to the division number of subchannels, posing a challenge for high frequency utilization efficiency and reducing FEC calculation amount.
Innovation Solution
A decoding circuit and method that distributes decoding metrics to multiple lanes, utilizing first and second likelihood calculation circuits to calculate logarithmic likelihood ratios and perform hard decisions, combined with an outer code decoder to reduce operation complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SD-FEC is applied to subchannels with small communication channel capacity in CP-MLC, then FEC calculation amount is reduced, but operation amount of likelihood calculation exponentially increases with division number of subchannel
Solution Approach 1:
The decoding process is segmented into multiple lanes, where each lane handles a specific subset of the decoding metric calculation. The distributor divides the decoding metric into multiple lanes, and each lane performs parallel likelihood calculation, thereby distributing the computational burden and reducing the exponential operation amount in a single lane.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by organizing the likelihood calculation across multiple lanes instead of concentrating it in a single sequential process. This dimensional transformation from single-lane sequential processing to multi-lane parallel processing effectively reduces the operation amount in each individual lane while maintaining overall decoding performance.
2Adaptability or versatility
If division number of subchannel is increased to improve frequency utilization efficiency, then FEC performance is improved, but operation amount of likelihood calculation exponentially increases
Solution Approach 1:
By segmenting the likelihood calculation across multiple lanes, the system can handle higher division numbers of subchannels without exponential complexity growth in each lane. Each lane processes a portion of the total computation, enabling the system to scale with increased division numbers while maintaining manageable operation amounts per lane.
Solution Approach 2:
The multi-lane architecture adds a spatial dimension to the processing structure, allowing the system to accommodate higher division numbers by distributing computations across parallel processing paths rather than increasing complexity within a single processing path.
Data Source
AI summary
Provided is a decoding circuit used for coherent digital signal processing, including: a distributor that distributes a decoding metric obtained by demodulating transmission data transmitted from a transmission device to each of a plurality of lanes on the basis of information on noise generated in a communication channel and a received signal; a first likelihood calculation circuit that is provided in one of the plurality of lanes and calculates a first logarithmic likelihood ratio using the decoding metric distributed by the distributor; a decoding unit that performs error correction decoding using the first logarithmic likelihood ratio and acquires an error-corrected code word; one or more second likelihood calculation circuits that are provided in a lane different from the lane in which the first likelihood calculation circuit is provided among the plurality of lanes, calculate a second logarithmic likelihood ratio on the basis of the decoding metric distributed by the distributor and the acquired code word, and perform hard decision; a combining unit that combines an output of the decoding unit and an output of the one or more second likelihood calculation circuits; and an outer code decoding unit that decodes an outer code.