Multilane Ethernet Synchronization via Segmented Markers
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Solution Overview
Problem
Existing integrated circuits and interface devices struggle to support high data rates proposed by the IEEE 802.3ba task force, such as 40 Gb and 100 Gb links, due to bandwidth limitations and synchronization issues across multiple data transfer lanes in Ethernet communication networks.
Innovation Solution
A multilane communication device with a physical coding sub-layer module that generates synchronization markers and data markers to align and transmit data blocks across multiple lanes, ensuring synchronization and efficient data transfer by splitting data streams into smaller sub-streams and using synchronization markers to restore alignment at the receiving end.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted over multiple lanes to achieve high data rates, then bandwidth is improved, but synchronization between lanes deteriorates
Solution Approach 1:
The patent segments the high-speed data stream into multiple parallel lanes for transmission. Each lane carries a portion of the data blocks, allowing the system to achieve high aggregate data rates while managing synchronization independently per lane using markers.
Solution Approach 2:
The patent introduces synchronization markers as intermediary elements that are inserted into the data stream on each lane. These markers act as mediators that enable the receiving end to detect and correct timing differences between lanes, thereby maintaining synchronization across multiple high-speed channels.
2Productivity
If data blocks are distributed across multiple lanes, then bandwidth utilization is improved, but data alignment deteriorates
Solution Approach 1:
The patent performs preliminary actions by inserting synchronization markers at predetermined intervals before data transmission begins. These pre-placed markers enable the receiving end to establish timing references in advance, ensuring that data blocks arriving from different lanes can be properly aligned without disruption to bandwidth utilization.
Solution Approach 2:
The patent implements a feedback mechanism where the receiving end detects synchronization markers and generates alignment information that is fed back to the deserialization process. This feedback loop continuously adjusts the timing of data block reconstruction, maintaining precise alignment even as data is distributed across multiple high-bandwidth lanes.
3Device complexity
If existing interface devices are used for high data rates, then device complexity is reduced, but support for 40 Gb and 100 Gb links deteriorates
Solution Approach 1:
The patent segments the high-speed interface functionality into multiple lower-speed lanes, each handled by existing interface devices. By dividing the 40 Gb or 100 Gb stream into parallel lanes that existing devices can handle individually, the system achieves support for high data rates without requiring each individual interface device to be redesigned for higher speeds.
Solution Approach 2:
The patent merges the output of multiple parallel lanes at the receiving end to reconstruct the high-speed data stream. By combining the capabilities of several existing interface devices operating in parallel, the system achieves aggregate bandwidths of 40 Gb and 100 Gb while keeping individual device complexity manageable.
Data Source
AI summary
A multilane communication device and methods for using the multilane communication device. In one embodiment, a physical coding sub-layer module comprising includes multiple data transfer lanes in a port of a multi-lane Ethernet switch for transferring blocks of data between devices in the port. The physical coding sub-layer module further includes a synchronization marker generator for generating synchronization markers to be periodically transmitted over the multiple data transfer lanes. The physical coding sub-layer module further includes a data marker module configured to generate at least two data marker blocks from a respective portion of a synchronization marker and a respective portion of a block of data, and to provide the at least two data marker blocks to respective first and second ones of the multiple of data transfer lanes.