Multi-Lane Reconfigurable FEC for Flexible Error Correction
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Solution Overview
Problem
Existing data communication systems are inadequate for handling high-bandwidth applications, such as social networks that process large amounts of multimedia data, due to limitations in error correction and operational flexibility.
Innovation Solution
A reconfigurable forward-error-correction (FEC) module that can operate in multiple modes, processing data from two or more communication lanes, either combining data for joint error correction or correcting data independently, eliminating the need for redundant hardware and supporting various communication modes without additional hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate FEC modules are used for each communication lane, then error correction reliability is improved, but device complexity and hardware costs increase
Solution Approach 1:
The patent combines multiple FEC processing functions into a single reconfigurable FEC module that can handle data from multiple communication lanes. The module includes a syndrome computation unit, key equation solver, and Chien search unit that can process data from 1, 2, 4, or 8 lanes by configuring the data width parameter, eliminating the need for separate FEC modules for each lane while maintaining error correction reliability
Solution Approach 2:
The reconfigurable FEC module is designed with multi-functionality to perform error correction for different numbers of communication lanes (1, 2, 4, or 8 lanes) using the same hardware structure. By adjusting the data width parameter and configuring the processing units, a single module replaces multiple dedicated FEC modules, reducing hardware complexity while maintaining universal error correction capability
2Adaptability or versatility
If multiple FEC modules are used to support different communication modes, then adaptability is improved, but hardware costs and device complexity increase
Solution Approach 1:
The FEC module incorporates dynamic reconfigurability through a data width parameter that can be adjusted at runtime to support different communication modes (1, 2, 4, or 8 lanes). The processing units including syndrome computation, key equation solver, and Chien search can dynamically adapt their operation based on the configured data width, allowing a single module to replace multiple static FEC modules designed for specific lane configurations
Solution Approach 2:
The module is designed as a universal FEC processor that can handle various communication lane configurations (1, 2, 4, or 8 lanes) through parameter configuration rather than requiring separate hardware instances. The same core processing units are reused across different modes by adjusting the data width parameter, achieving multi-mode support without increasing hardware complexity
3Speed
If FEC modules are designed for high-speed operation, then communication speed is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The high-speed FEC processing is achieved by segmenting the work across multiple communication lanes (1, 2, 4, or 8 lanes) that can be processed in parallel by the reconfigurable module. The syndrome computation unit calculates syndromes for each lane separately, then the key equation solver and Chien search unit process the combined data, enabling high-speed operation through parallel processing while maintaining a single modular hardware structure
Data Source
AI summary
The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.