Multi-Lane Link Error Detection with Per-Lane CRC Isolation
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Solution Overview
Problem
Current Ethernet protocols and InfiniBand link-layer implementations lack inherent facilities for reliable data transmission, leading to increased processing overhead and latency due to the need for explicit ACKs, which consume link bandwidth and add complexity, especially in high-performance computing environments where data transfer latencies are a significant bottleneck.
Innovation Solution
The proposed architecture introduces a lane error detection and removal mechanism using implicit ACKs with a replay buffer and per-lane CRCs to ensure reliable data transmission across multi-lane links, reducing the probability of data corruption and improving link reliability without explicit acknowledgments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If explicit ACKs are used for reliable data transmission, then data reliability is improved, but processing overhead and latency increase
Solution Approach 1:
The patent extracts the reliability assurance function from the explicit ACK mechanism and implements it through implicit ACKs using sequence numbers and replay buffers. The receiver implicitly acknowledges receipt by successfully processing and buffering data, eliminating the need for separate ACK packets while maintaining reliability.
Solution Approach 2:
The replay buffer acts as an intermediary mechanism that provides reliability without explicit ACKs. It stores transmitted data and allows the sender to retransmit if needed, mediating between the sender and receiver to ensure reliable delivery while reducing protocol complexity.
2Reliability
If explicit ACKs are used for reliable data transmission, then data reliability is improved, but link bandwidth is consumed
Solution Approach 1:
The patent removes the dedicated ACK packet from the communication stream and embeds acknowledgment functionality within the data packets themselves through sequence numbers and replay buffer mechanisms, eliminating additional bandwidth consumption for ACKs.
Solution Approach 2:
The patent merges the data transmission and acknowledgment functions into a single process. The successful reception and buffering of data serves as implicit acknowledgment, combining what were previously separate communication activities into one efficient operation.
3Reliability
If per-lane CRCs are used for error detection, then data integrity is improved, but processing complexity increases
Solution Approach 1:
The patent segments the error detection mechanism by implementing separate CRC checks for each lane independently. This allows parallel processing of CRC calculations across multiple lanes, improving data integrity detection while managing complexity through modular, lane-specific implementation.
Solution Approach 2:
The patent applies different quality levels of error detection to different lanes based on their individual characteristics. Per-lane CRCs allow each lane to be monitored and evaluated independently, providing localized error detection that adapts to specific lane conditions without requiring complex global error detection mechanisms.
4Speed
If multi-lane links are used for high-speed data transfer, then data transfer speed is improved, but probability of data corruption increases
Solution Approach 1:
The patent segments the multi-lane link into independently monitored lanes, each with its own CRC validation. This segmentation allows high-speed parallel transmission while providing granular error detection capability, identifying which specific lane(s) may be corrupted without affecting overall transmission speed.
Solution Approach 2:
The patent implements feedback mechanisms through implicit acknowledgments and replay buffers that monitor data integrity across all lanes. When errors are detected in specific lanes, the system can request retransmission of affected data, providing continuous feedback that maintains reliability despite high-speed multi-lane operation.
Data Source
AI summary
Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.