Multilane Link Deskew FIFO for Low-Latency Clock Domain Crossing
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Solution Overview
Problem
Conventional systems face challenges in minimizing latency and inefficiencies when crossing clock domains in multilane data links due to signal skewing and the need for additional clock domain crossing buffers, which is critical in applications like financial trading where order processing timing is crucial.
Innovation Solution
The solution involves clocking data streams into FIFO deskew buffers using recovered clock signals and then outputting them using the target clock domain signal, eliminating the need for a separate clock domain crossing buffer, thereby synchronizing data streams with both the target clock signal and each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock domain crossing with separate FIFO buffers is used for each lane, then data synchronization between clock domains is achieved, but latency is increased and processing cycles are extended
Solution Approach 1:
The patent merges the deskew buffer and clock domain crossing buffer into a single unified FIFO structure. Instead of using separate buffers for deskewing and clock domain crossing, the invention combines these functions into one buffer that performs both operations simultaneously, thereby reducing latency and processing cycles while maintaining data synchronization reliability.
Solution Approach 2:
The unified FIFO buffer serves multiple functions: it acts as both a deskew buffer to align skewed data from multiple lanes and as a clock domain crossing buffer to transfer data between different clock domains. This multi-functionality eliminates the need for separate buffers and reduces overall system latency.
2Reliability
If multiple separate FIFO buffers are used for deskewing and clock domain crossing, then data integrity is maintained, but device complexity increases
Solution Approach 1:
The patent combines multiple separate FIFO buffers (deskew buffer and clock domain crossing buffer) into a single unified buffer structure. This merging reduces device complexity by eliminating redundant buffer components while maintaining data integrity through the unified buffer's ability to handle both deskewing and clock domain crossing functions.
3Reliability
If conventional multilane deskewing process is used, then signal skew is corrected, but processing cycles are increased
Solution Approach 1:
The unified FIFO buffer enables continuous operation by performing deskewing and clock domain crossing in a single continuous process rather than in separate discrete steps. This continuity eliminates idle cycles between operations and maintains steady data flow, thereby improving processing speed while ensuring signal synchronization.
Data Source
AI summary
Systems and methods for communicating data via a multilane data link from a first clock domain a second clock domain, where the data streams of a multilane link are clocked into FIFO deskew buffers using clock signals that are recovered from the data streams themselves. Each data stream is clocked into the deskew buffer with the clock signal recovered from that data stream. The data is clocked out of the deskew buffers using the clock signal of a target clock domain so that the data streams clocked out of the deskew buffers are synchronized with each other and with the clock signal of the target clock domain (the target clock signal) to eliminate the need for a separate clock domain crossing buffer.