Multi-Lane Memory Compression for Lower CPU Occupancy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing systems, the CPU is often occupied with data compression and decompression tasks, leading to delays and reduced availability for other operations, especially in systems with multiple processors where only the CPU typically supports these operations, causing performance issues due to latency in data swapping between cache and persistent storage.
Innovation Solution
A processor with a compression/decompression unit that utilizes multiple hardware lanes to perform compression and decompression tasks concurrently, allowing the CPU to remain available for other operations by using a dictionary-based and statistical-based algorithm for efficient data processing and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the CPU performs data compression and decompression tasks, then data storage efficiency is improved, but the CPU becomes occupied and unavailable for other operations
Solution Approach 1:
The patent extracts the compression and decompression functionality from the CPU by implementing dedicated compression units within the cache memory structure. These specialized units handle compression tasks independently, allowing the CPU to focus on other operations while maintaining data storage efficiency through hardware-accelerated compression.
Solution Approach 2:
The patent introduces compression units as intermediary components between the CPU and cache memory. These units act as mediators that perform compression operations on data before it is stored in cache, reducing the computational burden on the CPU while ensuring efficient use of cache storage space.
2Volume of stationary object
If data is swapped between local cache memories and persistent storage, then storage capacity is sufficient, but latency increases and performance decreases
Solution Approach 1:
The patent applies preliminary compression to data before it is stored in cache memory. By compressing data in advance using dedicated compression units, the system reduces the volume of data that needs to be swapped between cache and persistent storage, thereby reducing access latency and improving overall performance.
Solution Approach 2:
The patent changes the physical state of data by compressing it, thereby altering its volume parameter. This compression allows more data to be stored in the same cache memory space, reducing the frequency and amount of data swapping required with persistent storage, and consequently reducing access latency.
3Adaptability or versatility
If the CPU is the only processor supporting compression operations, then compression capability is available, but other processors incur delays waiting for the CPU
Solution Approach 1:
The patent extends compression capability to multiple processors by implementing compression units that are accessible by different processor types (CPU, GPU, DSP). This allows any processor to initiate compression operations without blocking, as the dedicated compression units handle the compression tasks independently, enabling universal access to compression functionality while maintaining high processor throughput.
Solution Approach 2:
The patent enables compression units to perform compression operations autonomously without requiring continuous CPU intervention. Once a compression operation is initiated by any processor, the compression unit executes the compression task independently, allowing the initiating processor to continue with other operations without waiting for compression to complete.
Data Source
AI summary
Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.