Multi-lane N-factorial Data Link Clock Recovery
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Solution Overview
Problem
There is a need for optimized communications and improved data transfer rates on multi-signal communications links, particularly in multi-lane, multi-wire data communication interfaces used in mobile devices, where existing methods often require separate clock channels and phase-locked loops to manage skew between clock and data signals.
Innovation Solution
The method involves receiving a sequence of symbols from a multi-lane interface, recovering a clock signal based on transitions in the signaling state of the wires, and using this clock signal to convert the symbols into data bits, with the option to derive additional data bits from a second lane without transcoding, allowing for efficient data transfer by embedding clock information within the symbol transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock channels and phase-locked loops are used to manage skew between clock and data signals, then clock signal recovery and timing synchronization are improved, but device complexity and circuit overhead increase
Solution Approach 1:
The patent merges the clock signal and data signals into a single multi-wire differential signaling channel. The clock information is embedded within the data signal transitions, eliminating the need for separate clock channels and phase-locked loops. This combining approach maintains reliable clock recovery while significantly reducing circuit complexity and overhead.
Solution Approach 2:
The data signal channel serves multiple functions simultaneously: it carries both data information and clock synchronization information. By making the data channel universal for both purposes, the patent eliminates dedicated clock recovery circuitry and achieves both data transmission and timing synchronization through a single channel infrastructure.
2Productivity
If multi-lane, multi-wire differential signaling is used to increase data transfer rates, then productivity is improved, but device complexity and signal management difficulty increase
Solution Approach 1:
The patent segments the data transmission into multiple parallel lanes, each carrying independent data streams. This segmentation allows parallel data transfer to increase overall throughput while keeping each individual lane manageable. The multi-wire differential signaling within each lane provides robustness without proportionally increasing complexity.
Solution Approach 2:
The patent utilizes differential signaling parameters (voltage levels, transition states) to encode multiple bits of information simultaneously across N wires. By changing the signaling parameters to support N-factorial encoding, the system achieves high data transfer rates without adding proportional complexity, as the encoding is performed at the signal level rather than requiring additional physical channels.
Data Source
AI summary
System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multi-lane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.