Multilane Transmitter Clock Staggering via Phase Lock Circuit

The patent introduces a dedicated delay circuit as an intermediary component between the clock signal source and the transmitter lanes. This delay circuit is specifically designed to provide precise, PVT-insensitive time staggering. The delay circuit includes multiple delay elements with equal delay times that are configured to receive clock signals and output staggered clock signals to different transmitter lanes, thereby mediating the timing adjustment function while being immune to PVT variations affecting the staggering performance.

The patent changes the design parameter of the delay circuit by ensuring all delay elements have equal delay times and are configured with specific connectivity patterns. This parameter standardization makes the delay circuit insensitive to PVT variations. The delay circuit is designed such that the relative timing relationships between output signals remain constant regardless of process, voltage, or temperature changes, thereby resolving the contradiction between timing accuracy and PVT sensitivity.

The patent segments the clock signal distribution by introducing a delay circuit that divides the single clock signal into multiple staggered clock signals for different transmitter lanes. This segmentation in time domain allows simultaneous operation of multiple lanes while preventing power bouncing superposition. Each lane receives its clock signal at a different time offset, causing power bouncing events to occur at different times and thus not superimpose on each other.

The patent employs periodic staggering of clock signals to multiple lanes. The delay circuit creates a periodic pattern where clock signals are distributed to different lanes in a sequential manner with fixed time intervals. This periodic action maintains the efficiency of multi-lane operation while systematically preventing the simultaneous occurrence of power bouncing effects across all lanes.