Multi-Layer Bottom Spacers for Uniform Low-Capacitance VTFETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing processes for fabricating vertical transfer field effect transistors (VTFETs) result in bottom spacers with defects and significant feature-to-feature variations, leading to decreased device yield and performance due to parasitic capacitance issues.
Innovation Solution
A self-aligned, multi-layer bottom spacer process is implemented, where each layer of the spacer has a distinct vertical height, with the outer layer being taller than the inner and middle layers, to effectively reduce parasitic capacitance while maintaining gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing processes are used to form bottom spacers in VTFETs, then the fabrication process is simple, but the bottom spacers suffer from defects and large feature-to-feature variations
Solution Approach 1:
The bottom spacer is divided into three distinct layers (inner layer, middle layer, outer layer) with different heights and materials. This segmentation allows each layer to be optimized independently for uniformity and performance, resolving the contradiction by transforming a single uniform structure into a multi-layered precision structure that achieves superior manufacturing precision through controlled complexity
Solution Approach 2:
Different regions of the bottom spacer are assigned different materials and heights: the inner layer near the fin uses one material configuration, the middle layer uses another, and the outer layer uses a third. This local differentiation enables precise control over parasitic capacitance at each location, achieving high manufacturing precision by tailoring properties to specific spatial requirements rather than using a uniform structure
2Object-affected harmful factors
If existing bottom spacer processes are used, then the fabrication is straightforward, but parasitic capacitance from the bottom source/drain structure is not adequately addressed
Solution Approach 1:
The bottom spacer transitions from a two-dimensional planar structure to a three-dimensional multi-layered structure with varying heights. The inner, middle, and outer layers extend to different vertical levels, creating a stepped profile that provides enhanced isolation from the bottom source/drain structure in multiple spatial dimensions, thereby more effectively reducing parasitic capacitance while maintaining uniformity
Solution Approach 2:
The bottom spacer employs composite construction with three different materials or material combinations in the inner, middle, and outer layers. Each layer material is selected for specific electrical and mechanical properties that collectively minimize parasitic capacitance effects, resolving the contradiction by using material composition diversity to achieve both low parasitic capacitance and high uniformity
3Reliability
If a single-layer bottom spacer is used, then the device structure is simple, but there are significant feature-to-feature variations that decrease device yield
Solution Approach 1:
The bottom spacer is segmented into three independently controlled layers, each with specific height and material properties. This segmentation enables precise control over the electrical characteristics and dimensional uniformity of each layer, reducing feature-to-feature variations and improving device yield through enhanced reliability, while the modular nature of the segmentation manages the complexity through systematic design
4Object-affected harmful factors
If the bottom spacer height is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but the gate length is compromised
Solution Approach 1:
The solution moves from increasing height uniformly in one dimension to creating a multi-level stepped structure in three dimensions. The inner, middle, and outer layers provide progressive isolation at different vertical levels, effectively reducing parasitic capacitance through three-dimensional spatial arrangement without extending the horizontal gate length, thereby resolving the contradiction by utilizing vertical stratification rather than horizontal or uniform vertical expansion
Data Source
AI summary
Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.