Multilayer Output Buffer for Image Processing Aberration Correction
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Solution Overview
Problem
Image processing systems face challenges with distortion aberration and chromatic aberration, particularly in wide-angle lenses, which require costly optical systems or inefficient image processing techniques, leading to frame delays, power consumption issues, and limited data transfer speed.
Innovation Solution
An image processing apparatus that employs a multilayered output buffer configuration with a buffer controller adding tag information including camera IDs and pixel addresses, enabling efficient distortion correction and chromatic aberration correction through time division processing and burst transfer, reducing buffer size and improving transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If image processing is performed through a DRAM, then image processing capability is improved, but frame delay occurs and data transfer speed is limited due to DRAM bandwidth
Solution Approach 1:
The patent divides the output buffer into multiple layers (first layer, second layer, third layer) to segment the buffering process. This allows different stages of image processing data to be handled in parallel across layers, reducing the time bottleneck that would occur in a single-layer sequential processing through DRAM.
Solution Approach 2:
The patent introduces a temporal dimension by implementing time-division multiplexing where the single image processing circuit processes multiple image pickup units at different time slots. The multilayer buffer structure provides additional spatial dimensions for data organization, allowing efficient data staging without requiring proportional increases in DRAM bandwidth.
2Productivity
If image processing is performed through a DRAM, then image processing capability is improved, but power consumption increases
Solution Approach 1:
By segmenting the buffer into multiple layers, the patent reduces the frequency of data transfers to and from DRAM. Each layer can be filled and emptied independently, allowing the system to batch operations and reduce the overall number of high-power DRAM access cycles, thereby lowering power consumption while maintaining processing capability.
Solution Approach 2:
The multilayer output buffer acts as an intermediary between the image processing circuit and the DRAM. It allows data to be staged and prepared in the buffer layers before being transferred to DRAM in optimized batches, reducing the total number of DRAM access operations and consequently reducing power consumption.
3Device complexity
If multiple image pickup units are processed with one image processing circuit in time division manner, then device complexity is reduced, but processing speed for each unit decreases
Solution Approach 1:
The patent implements preliminary action by pre-processing and staging data in the multilayer output buffer before final DRAM transfer. The first layer receives and preliminarily processes data from the image processing circuit, preparing it for subsequent transfer to the second and third layers. This preliminary staging allows the single image processing circuit to maintain higher effective processing speed by reducing idle wait time between processing different image pickup units.
4Use of energy by moving object
If buffer size is reduced, then power consumption decreases, but data transfer efficiency may be compromised
Solution Approach 1:
The multilayer buffer structure segments the buffering function across three distinct layers, each with optimized capacity. This segmentation allows the total buffer memory to be distributed efficiently, reducing the peak memory access requirements and power consumption while maintaining adequate capacity for data transfer operations. Each layer can be independently managed for optimal transfer efficiency.
Solution Approach 2:
By adding the layer dimension, the patent creates a three-dimensional buffer architecture (layer, row, column) that allows data to be organized and transferred more efficiently. This dimensional organization enables parallel transfer operations across layers, maintaining high data transfer efficiency even with reduced total buffer capacity compared to a single large buffer.
Data Source
AI summary
An image processing apparatus according to an embodiment includes a preprocessing circuit and a distortion correction circuit configured to process, in a time division manner, a plurality of images generated by a plurality of image pickup units and an output buffer circuit configured to buffer the processed plurality of images in a unit of a block and add an identification tag including an address and an identification ID to the block.