Multilayer Butterfly Network for Stream Alignment and Memory Bandwidth

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Solution Overview

Problem

Modern digital signal processors face challenges with increasing workloads, memory bandwidth limitations, and scheduling issues, particularly in real-time data processing, where memory access latency and reliability impact performance due to transistor scaling and complex software stacks.

Innovation Solution

A digital data processor with a streaming engine that retrieves a stream of instruction-specified data elements for processing, utilizing a multilayer butterfly network for data transformation and alignment, with precalculated inputs and simple combinatorial logic to generate control signals, reducing complexity and enabling parallel control calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a multilayer butterfly network is used for data transformation and alignment, then data processing capability and bandwidth are improved, but control circuit complexity increases

Engineering Contradiction:

Improvedata processing capabilityVSAvoidcontrol circuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The control of the multilayer butterfly network is segmented into multiple independent control signals, each managing specific multiplexer operations within the network. This segmentation allows complex data transformations to be broken down into manageable control stages, reducing the complexity of any single control circuit while maintaining overall processing capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Control signals for the butterfly network are precalculated based on input and output data patterns before execution. This preliminary calculation enables the control circuits to operate with simpler, pre-determined signal sequences rather than requiring complex real-time decision-making, thereby reducing control circuit complexity while preserving high data processing capability.

Inventive Principle:

Principle #10Preliminary action

2Quantity of substance

If memory access resources are increased to handle real-time data processing, then memory bandwidth is improved, but system complexity and cost increase

Engineering Contradiction:

Improvememory bandwidthVSAvoidsystem complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces a specialized data path dimension that bypasses traditional memory access bottlenecks. By creating a direct data movement pathway from input to output that operates parallel to the main processing units, the system achieves high memory bandwidth without proportionally increasing overall system complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The enhanced memory access resources are designed with multi-functionality, serving both real-time data processing requirements and general-purpose data access needs. This universal design allows the same hardware resources to fulfill multiple functions, improving effective bandwidth utilization without requiring separate dedicated resources for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If more functional units are added to increase processing throughput, then productivity is improved, but control logic complexity increases

Engineering Contradiction:

Improveprocessing throughputVSAvoidcontrol logic complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces intermediary control structures that mediate between multiple functional units and the central control logic. These intermediaries act as buffer layers that simplify the control signals received from functional units, reducing the complexity burden on the central control logic while enabling coordination of numerous processing units for high throughput.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Volume of moving object

If transistor size is reduced to increase integration density, then device miniaturization is achieved, but memory reliability deteriorates

Engineering Contradiction:

Improvedevice sizeVSAvoidmemory reliability

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent implements error detection and correction mechanisms that are built into the memory system architecture before failures occur. By incorporating redundancy and validation logic in advance, the system compensates for the reduced reliability inherent in smaller transistors, maintaining data integrity despite miniaturization.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11804858B2Butterfly network on load data return

Publication Date: 2023.10.31 TEXAS INSTRUMENTS INC

AI summary

A system, method, and device is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network that includes a plurality of layers of multiplexers. Many transformations are possible with such a network which may include separate control of each multiplexer.