Multilayer Capacitor Margin Structure for Crack Suppression
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Solution Overview
Problem
Multilayer ceramic capacitors face issues with cracks due to expansion and contraction of the dielectric layer when voltage is applied, leading to potential damage to the capacitance formation portion, especially in large thick film products under high voltage.
Innovation Solution
The multilayer electronic component incorporates a body with a dielectric layer and internal electrodes, featuring margin portions with specific grain size and Ti ion to Ba ion ratios in different regions to enhance the strength of the margin portions and alter the path of cracks, preventing them from transferring to the capacitance formation area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a perovskite material such as BaTiO3 is used in the dielectric layer to secure high dielectric constant, then the capacitance is improved, but cracks occur in the dielectric layer or at the interface between dielectric and internal electrode due to expansion and contraction under applied voltage
Solution Approach 1:
The patent introduces a margin portion with a specific grain structure (where G2>G1 and G2>G3) at the boundary between the capacitance formation portion and external surface. This local structural modification creates a transition zone with different mechanical properties that absorbs expansion/contraction stress, preventing crack propagation while maintaining the high dielectric constant material in the capacitance formation area.
2Reliability
If the dielectric layer undergoes expansion in thickness direction and contraction in width direction under applied voltage, then high capacitance is achieved, but cracks are generated in the dielectric layer
Solution Approach 1:
The patent modifies the grain size parameters in the margin portion by controlling sintering conditions to achieve G2>G1 and G2>G3. This parameter change creates a grain structure that can accommodate the dimensional changes (expansion in thickness, contraction in width) under applied voltage, thereby preventing crack formation while maintaining the piezoelectric and dielectric properties.
3Power
If large thick film products with high applied voltage are used, then high power applications are enabled, but the problem of cracks and interface fracture is more pronounced
Solution Approach 1:
The patent pre-configures the margin portion with a specific grain structure (G2>G1 and G2>G3) before the component is subjected to high voltage operation. This preliminary structural preparation ensures that when high voltage is applied, the expansion and contraction forces are already accommodated by the gradient grain structure, preventing interface fracture and crack propagation that would otherwise occur in large thick film products.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses the occurrence of cracks and improves the reliability of the multilayer electronic component by enhancing the strength of the margin portions and changing the crack path, thereby preventing damage to the capacitance formation portion.
Implementation Method 1
When voltage is applied to the multilayer electronic component at room temperature, expansion is performed in a thickness direction of the multilayer electronic component, and relative contraction is performed in a width direction thereof by a perovskite crystal structure of a material included in the dielectric layer
Data Source
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AI summary
A multilayer electronic component includes: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode disposed on the body, in which the body includes a capacitance formation portion and margin portions disposed on both surfaces of the capacitance formation portion in a width direction, the margin portions include a first region adjacent to the capacitance formation portion, a third region adjacent to an external surface of the margin portion, and a second region disposed between the first and third regions, and G2>G1 and G2>G3 when an average grain size of a dielectric grain included in the first region is referred to as G1, an average grain size of a dielectric grain included in the second region is referred to as G2, and an average grain size of a dielectric grain included in the third region is referred to as G3.