Multilayer Capacitor Dislocation Alignment
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Solution Overview
Problem
Multilayer ceramic capacitors face challenges in securing DC bias capacity and minimizing high-temperature effective capacity reduction due to grain size and grain growth, which complicates the integration and miniaturization of electronic devices.
Innovation Solution
A multilayer capacitor design with a dielectric layer having a dislocation ratio of 20% or greater, where dislocations are strategically positioned between grain boundaries, enhancing DC bias capacity and reducing high-temperature capacity loss by aligning ferroelectric and relaxor phases in the c-axis direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the grain size of the dielectric material is reduced to secure DC bias capacity, then the DC bias capacity is improved, but the dielectric constant decreases making it difficult to secure high capacitance
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the dielectric grains, specifically orienting the c-axis perpendicular to the electrode surfaces. This parameter change allows the use of larger grain sizes without sacrificing DC bias capacity, thereby resolving the contradiction between grain size reduction and dielectric constant maintenance
Solution Approach 2:
The patent employs a composite dielectric material system comprising barium titanate (BT) as the main component with added lead zirconate titanate (PZT) or lead magnesium zirconate titanate (PMZT) in specific proportions. This composite material approach enables simultaneous achievement of high dielectric constant and high DC bias capacity through synergistic material properties
2Reliability
If grain growth of the dielectric material is suppressed to maintain high core ratio and alleviate high-temperature capacity reduction, then high-temperature effective capacity is improved, but the grain size reduction causes decrease in dielectric constant
Solution Approach 1:
The patent changes the crystallographic orientation parameter by ensuring c-axis alignment perpendicular to electrodes, which fundamentally alters the temperature-stability characteristics of the dielectric material. This parameter change allows larger grain sizes while maintaining high-temperature capacity stability, resolving the contradiction between grain growth suppression and dielectric constant maintenance
Solution Approach 2:
The patent applies different material compositions to different regions of the dielectric layer, with the core region having specific BT-based composition and potential shell regions having modified compositions. This local quality differentiation allows optimization of both high-temperature stability and dielectric constant in respective regions
3Volume of moving object
If the dielectric layer is made thinner to implement smaller MLCC size, then the miniaturization is achieved, but the electric field increases requiring sufficient DC bias capacity which conflicts with grain size requirements
Solution Approach 1:
The patent changes the crystallographic orientation parameter (c-axis perpendicular to electrodes) and material composition parameters to fundamentally improve DC bias capacity characteristics. These parameter changes enable thin dielectric layers to maintain sufficient DC bias capacity, resolving the contradiction between miniaturization and DC bias capacity requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively improves DC bias capacity and minimizes high-temperature capacity reduction, maintaining a high core ratio without suppressing grain growth, thus supporting the integration and miniaturization of electronic devices.
Implementation Method 1
A dislocation within one of the plurality of grains may be disposed between a phase having a tetragonal crystal structure and a phase having a cubic crystal structure
Data Source
AI summary
A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes stacked with the dielectric layer interposed therebetween and external electrodes disposed on an exterior of the body and connected to the internal electrodes. At least one of the plurality of dielectric layers includes a plurality of grains, and a ratio of grains having dislocations, among the plurality of grains, is 20% or greater.