Multilayer Thin-Film Capacitor Edge Via Design
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Solution Overview
Problem
Next-generation application processors require thinner and lighter multilayer thin-film capacitors with lower equivalent series resistance (ESR) than traditional multilayer ceramic capacitors, but existing methods struggle to achieve this with thin film technology due to limited dielectric layers and inadequate electrical connection stability.
Innovation Solution
A multilayer thin-film capacitor design featuring a stacked structure with alternating internal electrode layers, dielectric layers, and strategically positioned edge and central vias connected to external electrodes, increasing via density and improving electrical connections to reduce ESR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If thin film technology is used to manufacture capacitors, then the capacitor can be thinner and lighter, but the number of dielectric layers is reduced making it difficult to achieve higher capacitance
Solution Approach 1:
The patent changes the geometric parameters of the via structures (increasing density, optimizing dimensions, and strategic placement) to improve electrical connection efficiency. This allows thin-film capacitors to achieve lower ESR values without increasing the number of dielectric layers, thereby maintaining the thin and light characteristics while improving electrical performance.
2Quantity of substance
If a large number of dielectric layers are stacked using thin film technology, then capacitance can be increased, but the equivalent series resistance (ESR) between metal electrode layers increases
Solution Approach 1:
The patent introduces a new dimensional approach by optimizing via placement in the planar direction (length and width dimensions) rather than only increasing via count vertically. By strategically positioning vias at edges and optimizing their distribution across the capacitor surface, the patent reduces current path length and ESR without requiring proportional increases in via density that would complicate manufacturing.
Solution Approach 2:
The patent applies different via configurations to different regions of the capacitor. Edge vias are positioned at specific locations along the periphery, while central vias are placed in the interior region. This localized optimization allows different areas to contribute differently to ESR reduction, with edge vias providing efficient current collection at boundaries and central vias providing additional parallel conduction paths in the bulk.
Data Source
AI summary
A multilayer thin-film capacitor includes a multilayer body in which a plurality of dielectric layers and first and second internal electrode layers are alternately stacked, and first and second external electrodes are disposed on the multilayer body and connected to the first and second internal electrode layers, respectively. The multilayer thin-film capacitor may include a first edge via connected to the external electrode and disposed at or adjacent at least one edge of an upper surface of the multilayer body, and a second edge via connected to the second external electrode and disposed at or adjacent at least one edge of the upper surface of the multilayer body.