Multilayer Capacitor ESL Reduction via End-Face Terminal Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multilayer ceramic capacitors have high equivalent serial inductance (ESL), which exacerbates power source voltage fluctuations due to increasing load current fluctuations and higher CPU operating frequencies, necessitating a reduction in ESL to maintain voltage stability, especially at low operating voltages and high current fluctuation rates.
Innovation Solution
A multilayer capacitor design with a dielectric body of alternately stacked dielectric and conductor layers, featuring strategically positioned terminal electrodes and lead portions to minimize ESL, where the ratio of lead length to conductor layer length and spacing is optimized to achieve reduced ESL without increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multilayer ceramic capacitor structure is used, then manufacturing is simple, but ESL is high causing voltage fluctuations
Solution Approach 1:
The patent changes the terminal electrode configuration from conventional side-face mounting to end-face mounting, utilizing a different spatial dimension. This dimensional change repositions the current flow path to pass through the stacked conductor layers more directly, reducing the loop area and thus lowering ESL while maintaining the simple layered manufacturing process
2Reliability
If multi-terminal capacitor is used to reduce ESL, then ESL is reduced, but manufacturing cost increases
Solution Approach 1:
The patent makes the existing two terminal electrodes serve multiple functions: they provide both the capacitor's electrical terminals and the current flow paths for minimizing ESL. By optimizing the conductor layer connections to these two terminals, the structure achieves low ESL without requiring additional terminal electrodes, thus avoiding increased manufacturing complexity and cost
3Speed
If CPU operating frequency is increased, then processing speed improves, but load current fluctuation increases causing voltage instability
Solution Approach 1:
The patent applies preliminary anti-action by designing the capacitor structure to preemptively counteract the harmful effects of high-frequency current fluctuations. The optimized conductor layer arrangement and terminal electrode positioning create low-inductance current paths that resist the voltage fluctuations caused by rapid load current changes, allowing the capacitor to effectively suppress voltage instability even at high CPU operating frequencies
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces ESL to less than 60 pH, stabilizing power source voltage and enabling the capacitor to function as a suitable decoupling capacitor, while maintaining low manufacturing costs by eliminating the need for multiple terminal electrodes.
Implementation Method 1
a dielectric body having an approximately rectangular parallelepiped shape formed by alternately stacking a plurality of dielectric layers, first conductor layers and second conductor layers
Data Source
AI summary
A multilayer capacitor includes a dielectric body formed by a plurality of dielectric layers, a first conductor layer, a second conductor layer, a first terminal electrode, and a second terminal electrode formed on a first side face of side faces of the dielectric body in parallel to a stacking direction Z. The first and second conductor layers respectively include first and second lead portions connected to the first and second terminal electrodes. A relation (a+c)/(b×n)≦0.035 is formed between a length “a” between the first and second lead portions in a vertical direction to the stacking direction Z, a length “b” between conductor layers positioned at both ends of the dielectric body in the stacking direction, a space length “c” between the first side face and the first conductor layer, a total number “n” of the conductor layers.