Multilayer Capacitor ESL Reduction via Non-Overlapping External Conductors

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Solution Overview

Problem

Conventional multilayer ceramic capacitors have high equivalent serial inductance (ESL), which exacerbates fluctuations in power source voltage due to increasing load current frequencies, and existing solutions either fail to sufficiently reduce ESL or incur high manufacturing costs.

Innovation Solution

A multilayer capacitor design featuring non-overlapping external conductor layers and strategically positioned terminal electrodes, with lead portions extending across multiple side faces to increase current flow channels, effectively reducing ESL by creating parallel inductor components and canceling magnetic fields.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional multilayer ceramic capacitor structure is used, then manufacturing process is simple, but equivalent serial inductance (ESL) is high

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidequivalent serial inductance
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The capacitor is divided into internal layer portion and external layer portion with distinct conductor layer configurations. The internal layers use overlapping conductor layers for capacitance, while external layers use non-overlapping conductor layers for low ESL, allowing each segment to optimize for its specific function

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the capacitor have different conductor layer structures optimized for their local function: internal layers have overlapping conductors for high capacitance density, while external layers have non-overlapping conductors for low inductance, achieving local optimization of electrical properties

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If multi-terminal structure is used to reduce ESL, then equivalent serial inductance decreases, but manufacturing cost increases

Engineering Contradiction:
Improveequivalent serial inductanceVSAvoidmanufacturing cost
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The external conductor layers serve dual functions: they provide low-inductance current paths for ESL reduction while also serving as terminal electrodes for electrical connection, eliminating the need for separate terminal structures and reducing manufacturing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The terminal electrodes are merged with the external conductor layers, combining the ESL-reduction function and the electrical connection function into a single structural element, simplifying the overall structure and reducing manufacturing steps

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If terminal electrodes are formed only on two end faces, then manufacturing is simple, but current flow channels are limited

Engineering Contradiction:
Improveterminal electrode configurationVSAvoidcurrent flow path length
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

Terminal electrodes are extended from traditional two-dimensional end-face placement to three-dimensional placement across multiple surfaces (end faces and side faces), creating additional current flow paths and reducing inductance through enhanced current distribution

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7394647B2Multilayer capacitor
Publication Date: 2008.07.01 TDK CORP
  • US7394647B2 patent drawing
  • US7394647B2 patent drawing
  • US7394647B2 patent drawing

AI summary

A multilayer capacitor 10 of the present invention including: a dielectric body 12 formed by stacking a plurality of dielectric layers 12a; an internal layer portion 17 in which a first and second internal conductor layers 21 and 22 are stacked alternately in the dielectric body 12 via the dielectric layer 12a; external layer portions 19a and 19b in which a first and second external conductor layers 23 and 25 are stacked via the dielectric layer 12a; a first terminal electrode 31 connected with the first internal conductor layer 21 and the first external conductor layer 23, formed at least on a first side face 12A of the dielectric body 12; and a second terminal electrode 32 connected with the second internal conductor layer 22 and the second external conductor layer 25, formed at least on a second side face 12 B opposed to the first side face 12A.