Multilayer Capacitor ESL Reduction via Internal Conductor Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multilayer ceramic capacitors have high equivalent serial inductance (ESL), which exacerbates fluctuations in power source voltage due to increasing load current frequencies, and existing solutions like multi-terminal capacitors increase manufacturing costs.
Innovation Solution
A two-terminal multilayer capacitor design with a dielectric body and internal conductor layers, featuring branch lead patterns and strategically placed space patterns to cancel magnetic fields, reducing parasitic inductance and ESL while maintaining low manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional multilayer ceramic capacitor structure is used, then manufacturing process is simple, but equivalent serial inductance (ESL) is high
Solution Approach 1:
The internal conductor layer is segmented into multiple regions (first conductor region, second conductor region, third conductor region) with different connection configurations. This segmentation allows current to flow through multiple paths, reducing the overall equivalent serial inductance while maintaining a standard two-terminal capacitor structure that is easy to manufacture.
Solution Approach 2:
Different regions of the internal conductor layer are designed with different electrical characteristics. The first conductor region connects to both terminals, the second region connects only to the first terminal, and the third region connects only to the second terminal. This local differentiation optimizes current distribution to minimize ESL without complicating the overall manufacturing process.
2Object-affected harmful factors
If multi-terminal capacitor is used to reduce ESL, then equivalent serial inductance is reduced, but manufacturing cost increases
Solution Approach 1:
The standard two-terminal capacitor structure is made multi-functional by incorporating internal conductor regions that serve multiple purposes: the first conductor region provides low-inductance current path, while the second and third regions provide additional current distribution paths. This allows a conventional two-terminal capacitor to achieve ESL reduction normally requiring multi-terminal configurations, without increasing manufacturing complexity or cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces ESL, effectively stabilizing power source voltage and suitable for use as a decoupling capacitor, while minimizing manufacturing expenses.
Implementation Method 1
featuring branch lead patterns and strategically placed space patterns to cancel magnetic fields, reducing parasitic inductance and ESL
Data Source
AI summary
A multilayer capacitor includes a dielectric body 12 formed by stacking a plurality of dielectric layers 12a; a first internal conductor layer 21 led out straddling three side faces 12A, 12C and 12D of said dielectric body 12; a second internal conductor layer 22, stacked in the dielectric body 12 via dielectric layers 12a to the first internal conductor layer 21, led out straddling three side faces 12B, 12C and 12D; a first and a second terminal electrodes 31 and 32 formed on an outer face of said dielectric body 12, straddling the three side faces 12A, 12C and 12D, and 12B, and 12C and 12D, respectively. A first space pattern 41 is formed on the first lead portion at a position along with the first side face 12A, not connected with the first terminal electrode 31.