Multilayer Chip Capacitor with Four-Side Electrodes for Low ESL
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Solution Overview
Problem
Conventional multilayer chip capacitors face challenges in reducing size while maintaining low equivalent series inductance (ESL), especially when downsized, which leads to increased overall impedance when connected in parallel due to reduced external terminals and increased ESL per capacitor.
Innovation Solution
A multilayer chip capacitor design with a capacitor body having a length at least 2.5 times its width, featuring multiple pairs of external electrodes of different polarities on longer sides, and internal electrodes arranged alternately to interpose dielectric layers, effectively canceling mutual inductance and reducing ESL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the capacitor size is reduced, then the mounting area is increased, but the ESL increases due to fewer external terminals
Solution Approach 1:
The patent transitions from arranging external terminals only on the longer sides to arranging them on all four sides of the capacitor body. This dimensional expansion allows maintaining a high number of terminals even in reduced-size capacitors, thereby keeping ESL low while achieving compact dimensions suitable for small mounting areas.
Solution Approach 2:
The patent segments the terminal arrangement across multiple faces of the capacitor body rather than concentrating them on fewer sides. By distributing external terminals on all four sides, the design maintains effective terminal count and low ESL even when the overall capacitor size is reduced.
2Object-generated harmful factors
If more external terminals are arranged on one side, then the ESL is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric terminal arrangement where an odd number of external terminals are placed on each longer side while even numbers are placed on the shorter sides. This asymmetric distribution optimizes current path symmetry and magnetic flux cancellation, achieving low ESL while maintaining manufacturability through systematic rather than random placement patterns.
3Productivity
If the capacitor is downsized for higher density mounting, then the mounting area efficiency is improved, but the impedance stabilization performance deteriorates
Solution Approach 1:
By extending terminal arrangement to all four sides of the capacitor body, the patent maintains effective terminal count and low ESL in reduced-size capacitors. This enables high mounting density while preserving impedance stabilization performance, as each capacitor continues to function effectively despite smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for a smaller-sized capacitor with reduced ESL, enabling a greater number of capacitors to be connected in parallel on a limited mounting area, resulting in lower total inductance and improved impedance stabilization for high-frequency circuits.
Implementation Method 1
a multilayer chip capacitor including a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other
Implementation Method 2
a capacitor body having a plurality of dielectric layers deposited therein
Implementation Method 3
the first and second external electrodes on each of the longer sides arranged alternately with each other... cancel out magnetic fluxes generated by high frequency currents, thereby decreasing the ESL
Data Source
AI summary
A multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is 2.5 times greater than a width thereof.