Multilayer Capacitor Electrode Layout for Low ESR and Inductance
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Solution Overview
Problem
Existing multilayer capacitors face challenges in achieving low equivalent series resistance and inductance, particularly in high-speed environments, due to rapid changes in electronics industry demands for miniaturization and increased functionality.
Innovation Solution
A multilayer capacitor design with specific configurations of internal electrode layers and external terminals, including lead tabs and co-planar electrodes, to minimize equivalent series resistance and inductance, especially at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multilayer capacitor designs are used, then manufacturing is simpler, but equivalent series resistance and inductance are higher
Solution Approach 1:
The internal electrodes are segmented into multiple separate electrodes within each internal electrode layer, rather than using a single continuous electrode. This segmentation allows for optimized current distribution and reduced equivalent series resistance by creating multiple parallel current paths through the capacitor structure.
Solution Approach 2:
The electrode design extends into the vertical dimension with electrodes protruding from both top and bottom surfaces of the dielectric layers. This three-dimensional electrode arrangement creates additional current paths and reduces inductance by minimizing current loop areas, thereby improving high-frequency performance.
2Reliability
If conventional multilayer capacitor designs are used, then device structure is simpler, but equivalent series inductance is higher
Solution Approach 1:
The internal electrodes are segmented into multiple separate electrodes within each internal electrode layer, rather than using a single continuous electrode. This segmentation allows for optimized current distribution and reduced equivalent series resistance by creating multiple parallel current paths through the capacitor structure.
Solution Approach 2:
The electrode design extends into the vertical dimension with electrodes protruding from both top and bottom surfaces of the dielectric layers. This three-dimensional electrode arrangement creates additional current paths and reduces inductance by minimizing current loop areas, thereby improving high-frequency performance.
3Volume of moving object
If capacitor size is reduced for miniaturization, then device density increases, but performance in high-speed environments deteriorates
Solution Approach 1:
Multiple electrode structures are nested within compact dielectric layers, with each internal electrode layer containing multiple electrodes that protrude from opposite surfaces. This nested arrangement maximizes the number of effective capacitor elements within a minimal volume, maintaining low equivalent series resistance and inductance despite miniaturization.
Solution Approach 2:
The electrode design extends into the vertical dimension with electrodes protruding from both top and bottom surfaces of the dielectric layers. This three-dimensional electrode arrangement creates additional current paths and reduces inductance by minimizing current loop areas, thereby improving high-frequency performance.
Data Source
AI summary
The present invention is directed to a multilayer capacitor, a circuit board containing the multilayer capacitor, and an integrated circuit package containing the multilayer capacitor. A multilayer capacitor includes a body containing alternating dielectric layers and internal electrode layers that each include a first electrode and a second, co-planar electrode, the first electrode having a main body with at least one lead tab extending from each of a top edge and a bottom edge thereof. The capacitor also includes a first external terminal and a second external terminal that each wrap from a top surface, along an end surface, to a bottom surface. The first external terminal is electrically connected to the first electrode of the first internal electrode layers along its lead tab leading edges, and the second external terminal is electrically connected to the first electrode of the second internal electrode layers along its lead tab leading edges.


