Multilayer Capacitor Offset Edge Precision Control
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Solution Overview
Problem
Precision control over the capacitance of multilayer capacitors, especially in high-frequency applications, is challenging due to the difficulty in precisely controlling the capacitive area, which is crucial for achieving the required low capacitance values necessary for high-frequency signals like those in 5G spectrum frequencies.
Innovation Solution
A multilayer electronic device design that includes a capacitor with a precisely controlled capacitive area, achieved by stacking dielectric layers and forming conductive layers with a protrusion or recess within the overlapping area, allowing for precise adjustment of the overlapping area and capacitance through the use of offset edges and parallel edges, enabling precise control over the capacitive area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a very small capacitive area is used to achieve low capacitance values for high-frequency applications, then the capacitance precision is improved, but the manufacturing difficulty increases
Solution Approach 1:
The patent introduces a third dimension (Z-direction stacking) to control capacitance. By stacking multiple dielectric layers with conductive layers in between, the capacitive area can be precisely controlled through the overlapping area of conductive layers on different layers, rather than relying solely on planar dimensions. This dimensional approach allows for better precision in achieving very small capacitance values.
Solution Approach 2:
The capacitor is divided into multiple segments across different dielectric layers. Each conductive layer on a different dielectric layer forms a segment of the overall capacitor structure. The total capacitance is the sum of capacitances from each overlapping pair, allowing for modular control and precise adjustment of the total capacitive value by adjusting individual overlapping areas.
2Quantity of substance
If the capacitive area is reduced to achieve low capacitance values, then the capacitance value is improved, but the control over the overlapping area becomes more difficult
Solution Approach 1:
The patent uses vertical stacking of multiple dielectric layers to achieve precise control over the overlapping area. Instead of relying on a single large planar overlap, the capacitive area is distributed across multiple layers, each contributing a portion of the total capacitance. This allows for better control and easier manufacturing of very small capacitance values.
Solution Approach 2:
The patent employs offset edges and adjustable overlapping configurations that allow for dynamic control of the capacitive area. The conductive layers can be positioned with specific offsets relative to each other, enabling fine-tuning of the overlapping area and thus the capacitance value, even at very small scales required for high-frequency applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for precise control over the capacitance of the capacitor, achieving the required low capacitance values for high-frequency applications with improved precision and performance, including low insertion loss and consistent performance across a wide range of temperatures.
Implementation Method 1
The second conductive layer may overlap the first conductive layer in the X-Y plane at an overlapping area to form a capacitor
Implementation Method 2
a plurality of dielectric layers stacked in a Z-direction that is perpendicular to an X-Y plane
Data Source
AI summary
A multilayer electronic device may include a plurality of dielectric layers stacked in a Z-direction that is perpendicular to an X-Y plane. The device may include a first conductive layer overlying one of the plurality of dielectric layers. The multilayer electronic device may include a second conductive layer overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer in the Z-direction. The second conductive layer may overlap the first conductive layer in the X-Y plane at an overlapping area to form a capacitor. The first conductive layer may have a pair of parallel edges at a boundary of the overlapping area and an offset edge within the overlapping area that is parallel with the pair of parallel edges. An offset distance between the offset edge and at least one of the pair of parallel edges may be less than about 500 microns.