Multilayer Capacitor with Segmented Conductor Arrangements
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Solution Overview
Problem
Ultra-small multilayer capacitors face difficulties in achieving desired electrostatic capacitance due to increased change rates with reduced ceramic layers, limited electrode position adjustments, and space constraints, making it challenging to obtain precise capacitance using conventional adjustment methods.
Innovation Solution
A manufacturing method involving the alternation of conductor and dielectric layers in specific arrangements, with less than 50 conductor layers, and the use of effective and ineffective dielectric layers to control electrostatic capacitance, along with stretching and bending of conductor layers to form outer electrodes, results in a multilayer capacitor with desired capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the number of laminated ceramic layers is reduced to achieve ultra-small size, then the device size is decreased, but the electrostatic capacitance control precision deteriorates due to increased change rate per layer
Solution Approach 1:
The patent segments the conductor layers into two distinct arrangements (first and second arrangements) with different patterns. This segmentation allows independent control of capacitance contributions from different layer groups, enabling precise capacitance adjustment even with fewer total layers. The laminate includes conductor layers in a first arrangement and conductor layers in a second arrangement, where the arrangements differ in their electrode positioning patterns.
Solution Approach 2:
The patent applies local quality by creating different conductor layer arrangements in different regions of the laminate. The first arrangement has conductors positioned to provide certain capacitance characteristics, while the second arrangement has conductors positioned differently to provide complementary characteristics. This allows fine-tuned control of overall capacitance by adjusting the number and configuration of layers in each arrangement.
2Manufacturing precision
If the distance between electrodes is increased or decreased to adjust electrostatic capacitance, then the capacitance value changes, but the adjustment range is limited by the ultra-small device dimensions
Solution Approach 1:
The patent transitions from adjusting capacitance primarily through vertical dimension (layer thickness and number) to utilizing the horizontal dimension (lateral positioning of electrodes). By creating two arrangements with different lateral electrode positions, the patent enables capacitance adjustment through planar configuration rather than just vertical stacking, effectively using another dimension for capacitance control.
3Manufacturing precision
If the positions of electrode pairs are shifted to adjust the opposed area, then the electrostatic capacitance changes, but the available space for position shifting is reduced in ultra-small devices
Solution Approach 1:
The patent employs asymmetry by creating two distinct conductor layer arrangements with different positional configurations. The first arrangement has conductors positioned asymmetrically relative to the second arrangement, allowing each arrangement to contribute differently to the overall capacitance. This asymmetric design enables capacitance adjustment through the combination and number of layers in each arrangement, maximizing the use of limited space.
Data Source
AI summary
A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.