Multilayer Capacitor Segmented Electrodes Reduce ESL
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Solution Overview
Problem
High-performance large scale integrated circuits (LSIs) face reduced system stability due to increased power supply noise and voltage fluctuations, which is exacerbated by high frequency power impedance, particularly influenced by the equivalent series inductance (ESL) of decoupling capacitors.
Innovation Solution
A multilayer capacitor design with alternately disposed internal electrodes and dielectric layers, exposed external electrodes, and conductive resin layers, mounted on a board, which reduces ESL and improves power impedance across a wide frequency band.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional decoupling capacitor design is used, then manufacturing is simpler, but ESL is higher and power impedance increases
Solution Approach 1:
The capacitor body is divided into multiple segments with alternating first and second internal electrodes disposed between opposing side surfaces. This segmentation allows current to flow through multiple parallel paths, reducing ESL while maintaining a manageable structural complexity through modular electrode arrangement.
Solution Approach 2:
The patent transitions from conventional top-bottom electrode arrangement to a multi-dimensional configuration where electrodes are exposed through and connected to side surfaces of the capacitor body. This dimensional change enables shorter current paths and lower ESL without significantly increasing overall device complexity.
2Use of energy by moving object
If driving voltage is lowered to decrease power, then power consumption is reduced, but system stability against power supply noise is reduced
Solution Approach 1:
The patent changes the electrical parameters of the decoupling capacitor by reducing ESL through its unique electrode configuration. This parameter change allows the capacitor to effectively suppress power supply noise even at lower operating voltages, maintaining system stability while enabling reduced power consumption in high-performance LSI systems.
3Productivity
If processing speed and functions are increased, then performance is improved, but power supply noise and voltage fluctuations increase
Solution Approach 1:
The segmented electrode structure creates multiple parallel current paths that reduce the overall inductance of the capacitor. This segmentation enables the capacitor to respond more effectively to high-frequency power supply noise generated by increased processing speeds and complex functions, suppressing noise without limiting performance improvements.
Solution Approach 2:
The patent employs a practical, manufacturable capacitor design that provides effective noise suppression for high-performance applications. The structure uses standard materials and processes to create a cost-effective solution that handles the power supply noise challenges of modern high-speed LSIs without requiring exotic or overly complex components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayer capacitor effectively reduces ESL, thereby stabilizing power supply noise and improving system stability in high-performance LSIs by absorbing current and voltage variations, enhancing the reliability of the power circuit.
Implementation Method 1
a multilayer capacitor includes a capacitor body including dielectric layers and a plurality of first internal electrodes and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween
Data Source
AI summary
A multilayer capacitor includes a capacitor body including a first surface and a second surface opposing each other, a third surface and a fourth surface connected to the first surface and the second surface and opposing each other, and a fifth surface and a sixth surface, a first internal electrode of the first internal electrodes being exposed through the third surface and the fourth surface, a second internal electrode of the second internal electrodes being exposed through the fifth surface and the sixth surface, a first external electrode and a second external electrode disposed in the third surface and the fourth surface of the capacitor body, respectively, the first external electrode and the second external electrode connected to an exposed portion of the first internal electrode, a third external electrode and a fourth external electrode disposed in the fifth surface and the sixth surface of the capacitor body, respectively.