Multilayer Capacitor Segmented Electrodes Reduce ESR ESL
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Solution Overview
Problem
Multilayer capacitors face challenges in achieving high capacitance while minimizing equivalent series resistance (ESR) and equivalent series inductance (ESL), which are crucial for efficient power delivery in compact electronic devices.
Innovation Solution
The design involves a multilayer capacitor with a capacitor body comprising alternately stacked dielectric layers and internal electrodes, where via electrodes connect external electrodes to internal electrodes, optimizing electrode placement and structure to reduce ESR and ESL, and increasing the effective area of internal electrodes for higher capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of internal electrodes is increased to achieve high capacitance, then capacitance is improved, but equivalent series resistance (ESR) increases
Solution Approach 1:
The internal electrodes are divided into multiple groups (first internal electrodes and second internal electrodes) with different connection paths to external electrodes. This segmentation allows current to be distributed through multiple parallel paths, reducing the overall ESR while maintaining high capacitance through the increased number of electrode layers.
Solution Approach 2:
The patent transitions from a conventional single-layer electrode structure to a multi-layer stacked structure where electrodes are arranged in alternating patterns across multiple dielectric layers. This dimensional arrangement increases the effective electrode area and creates multiple current paths, simultaneously improving capacitance and reducing ESR.
2Volume of moving object
If the capacitor size is reduced to fit compact devices, then device thickness is improved, but equivalent series inductance (ESL) increases
Solution Approach 1:
By segmenting the electrode connections into multiple groups with different connection paths, the current distribution is optimized to minimize loop areas. This reduces the parasitic inductance associated with each current path, allowing compact capacitor design without sacrificing electrical performance.
Solution Approach 2:
Via electrodes are introduced as intermediary connection elements between the internal electrodes and external electrodes. These via electrodes optimize the connection geometry and reduce the inductive effects by providing direct, short connection paths through the dielectric layers, enabling compact packaging with low ESL.
3Ease of operation
If via electrodes are added to connect internal electrodes to external electrodes, then electrode connectivity is improved, but device complexity increases
Solution Approach 1:
The via electrode connections are segmented into systematic groups corresponding to different internal electrode groups. This organized segmentation creates a modular connection architecture that, while more complex than simple connections, follows predictable patterns that simplify manufacturing and design processes.
Solution Approach 2:
Multiple via electrodes are merged into coordinated connection groups that collectively connect multiple internal electrodes to external electrodes. This merging approach consolidates the connection function into organized structures, managing complexity through functional integration rather than isolated connections.
Data Source
AI summary
A multilayer capacitor and a board on which the multilayer capacitor is mounted provide increased capacitor effective area. The multilayer capacitor includes a capacitor body having first and second dielectric layers each with first and second internal electrodes, first and second external electrodes disposed on a surface of the capacitor body, a first via electrode connecting the first internal electrodes to the first external electrode, and a second via electrode connecting the second internal electrodes to the second external electrode. The first and second dielectric layers are alternately stacked in the first direction such that the first internal electrode of the first dielectric layer overlaps the second internal electrode of the second dielectric layer in a first direction, and the second internal electrode of the first dielectric layer overlaps the first internal electrode of the second dielectric layer in the first direction.