Multilayer Capacitor Structure for HPCC Shape Distortion Control
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Solution Overview
Problem
High-Profile Ceramic Capacitors (HPCCs) face chip shape distortion due to stress during pressing and cutting processes, limiting the number of stacked layers that can be achieved while maintaining a compact form factor.
Innovation Solution
A multilayer electronic component design with an intermediate layer having a smaller grain size and lower porosity dielectric layer between capacitance formation portions, dispersing stress and preventing shape distortion, allowing for increased layer count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the chip is increased to achieve a high number of stacked layers, then the number of layers increases and high capacitance is achieved, but chip shape distortion occurs due to stress during pressing and cutting processes
Solution Approach 1:
The dielectric layer is segmented into multiple layers with different grain sizes and porosities. The first dielectric layer has smaller grains and lower porosity to resist stress, while the second dielectric layer has larger grains and higher porosity to maintain capacitance. This segmentation allows the structure to accommodate stress without distortion while achieving high layer counts.
Solution Approach 2:
Different regions of the dielectric layer are given different properties: the first dielectric layer (closer to internal electrodes) has smaller grains and lower porosity for stress resistance, while the second dielectric layer (outer region) has larger grains and higher porosity for capacitance contribution. This local quality differentiation resolves the contradiction between shape stability and capacitance.
2Quantity of substance
If the dielectric layer and internal electrodes are thinned to increase the number of layers, then high capacitance can be achieved with same chip dimensions, but technical limitations prevent easy implementation of high layer counts
Solution Approach 1:
Instead of uniformly thinning the dielectric layer, the invention changes the parameters (grain size and porosity) of different dielectric layers. The first dielectric layer maintains adequate thickness with smaller grains for stress resistance, while the second layer has larger grains for capacitance. This parameter differentiation enables high layer counts without excessive thinning challenges.
3Quantity of substance
If the chip is designed with thickness greater than width (HPCC structure), then high capacitance is achieved, but stress during pressing and cutting causes shape distortion
Solution Approach 1:
The dielectric structure is designed as a composite of two different dielectric layers with distinct properties. The first layer (smaller grains, lower porosity) provides mechanical strength and stress resistance, while the second layer (larger grains, higher porosity) provides high capacitance. This composite structure enables the HPCC form factor to achieve high capacitance without suffering from shape distortion.
Data Source
AI summary
A multilayer electronic component according to an example embodiment of the present disclosure may include: a body including a plurality of capacitance formation portions including first dielectric layers and internal electrodes alternately arranged in a first direction. An intermediate layer disposed is between the adjacent capacitance formation portions and includes a second dielectric layer. An external electrode is disposed on the body and connected to the internal electrode. The first and second dielectric layers may include a plurality of grains and pores. An average grain size of the first dielectric layer may be smaller than an average grain size of the second dielectric layer. A porosity of the first dielectric layer may be lower than a porosity of the second dielectric layer.