3D Multi-Layer Chip Integration via Metal Bump Interconnects
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Solution Overview
Problem
Wafer-Level Packaging (WLP) for IC chips faces challenges in manufacturability and structural reliability due to increasing electrical connections and lead count, which complicates the integration of multi-layer chips with high routing density and electromagnetic shielding.
Innovation Solution
The implementation of multi-layer chips within a multi-layer polymer structure using on-chip and intra-chip metal bumps, along with patterned metal layers, allows for electrical interconnection between chips and external circuits, enabling efficient manufacturing of multi-layer chip integration with high silicon utilization and electromagnetic shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Wafer-Level Packaging (WLP) is used to integrate multiple chips, then productivity and manufacturing efficiency are improved, but device complexity and structural reliability deteriorate due to increasing electrical connections and lead count
Solution Approach 1:
The patent transitions from planar 2D chip arrangement to 3D stacked configuration, enabling multiple chips to be vertically integrated through metal bump interconnections. This dimensional change allows high-density electrical connections without increasing lateral footprint, resolving the contradiction between manufacturing efficiency and electrical connection complexity
Solution Approach 2:
The patent implements a nested structure where multiple chip layers are stacked vertically with intermediate substrate layers, creating a compact hierarchical arrangement. This nesting approach consolidates numerous electrical connections into a compact 3D structure, improving productivity while managing connection complexity
2Manufacturing precision
If multiple conductive layers are added to increase device density, then manufacturing precision is improved, but device complexity and structural reliability worsen
Solution Approach 1:
The patent uses standardized metal bump structures replicated across multiple chip layers and substrate levels. This copying approach maintains consistent manufacturing precision for electrical interconnections while avoiding the complexity of designing unique conductive pathways for each layer, as identical bump structures can be manufactured using the same processes
3Area of moving object
If chip size is reduced to decrease package footprint, then weight and size are improved, but manufacturing precision and structural reliability deteriorate
Solution Approach 1:
The patent compensates for reduced chip area by utilizing the vertical dimension for stacking multiple chips. This dimensional transition allows compact package footprint while maintaining adequate manufacturing precision, as each individual chip can remain sufficiently large despite the overall reduced footprint achieved through vertical integration
Data Source
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AI summary
System-in packages, or multichip modules, are described which can include multi-layer chips in a multi-layer polymer structure, on-chip metal bumps on the multi-layer chips, intra-chip metal bumps in the multi-layer polymer structure, and patterned metal layers in the multi-layer polymer structure. The multi-layer chips in the multi-layer polymer structure can be connected to each other or to an external circuit through the on-chip metal bumps, the intra-chip metal bumps and the patterned metal layers. The system-in packages can be connected to external circuits through solder bumps, meal bumps or wirebonded wires.