Multilayer Chip Capacitor Segmented Units Flat Impedance
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Solution Overview
Problem
Existing multilayer chip capacitors face challenges in maintaining a constant impedance level in the power distribution network due to high frequency noise, particularly due to low equivalent series resistance (ESR) and high equivalent series inductance (ESL), which affects the stability of power circuits and increases the risk of voltage fluctuations.
Innovation Solution
A multilayer chip capacitor design featuring a capacitor body with alternating internal electrodes and external electrodes, where the first capacitor unit has a lower ESL and higher ESR than the second capacitor unit, and the two units are electrically isolated, allowing for controlled ESR through coupling conductor lines, maintaining a flat impedance curve across a wide frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor uses high-resistant materials in external and internal electrodes to increase ESR, then ESR increases, but localized heat spots occur due to current channeling through pinholes and ESR control becomes difficult
Solution Approach 1:
The capacitor is divided into multiple capacitor units with different ESR and ESL characteristics. The first capacitor unit has higher ESR and lower ESL, while the second capacitor unit has lower ESR and higher ESL. This segmentation allows the capacitor to achieve both high ESR and low ESL without using high-resistant materials that cause heat spots and ESR control difficulties.
Solution Approach 2:
Different regions of the capacitor have different electrical characteristics. The first capacitor unit is designed with specific electrode configurations to provide higher ESR and lower ESL, while the second capacitor unit provides lower ESR and higher ESL. This local differentiation of properties enables the overall capacitor to achieve the desired ESR and ESL characteristics without the harmful effects of using high-resistant materials throughout.
Data Source
AI summary
Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.