Multilayer Semiconductor Chip Identifier Allocation via Bit Train
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Solution Overview
Problem
Existing methods for setting chip identifiers in multilayer semiconductor devices require complex wiring configurations and may not guarantee unique or consecutively numbered identifiers, especially when semiconductor chips have different structures, leading to increased complexity and difficulty in implementing these technologies as the number of chips increases.
Innovation Solution
A semiconductor device configuration that includes an input terminal, a semiconductor device identifier hold block, a computation block, and an output terminal, which allows for the computation and updating of unique semiconductor device identifiers, reducing the number of wires needed for identifier setting by using a bit train mechanism and prohibiting updates based on predetermined values, enabling efficient identifier allocation even among chips with different structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip identifiers are set by wiring predetermined terminals to power or ground at package assembly, then chip identifiers can be allocated to each semiconductor chip, but the wiring configuration becomes complex and the number of wires increases with the number of chips
Solution Approach 1:
The patent extracts the chip identifier setting function from the wiring configuration by introducing a dedicated identifier setting circuit that operates independently of the global wiring system. This separates the identifier allocation task from the power/ground wiring, reducing wiring complexity while maintaining reliable identifier assignment.
Solution Approach 2:
The patent introduces an identifier setting circuit as an intermediary component between the power supply and the semiconductor chips. This mediator receives power through a simple wiring configuration and uses it to generate and allocate chip identifiers, thereby decoupling the wiring complexity from the identifier allocation function.
2Reliability
If increment circuits are sequentially connected in series to automatically set chip identifiers, then consecutive identifiers can be allocated, but the number of wires between layers increases corresponding to the number of chips
Solution Approach 1:
The patent merges multiple increment circuit functions into a single centralized identifier setting circuit. Instead of having separate increment circuits in each chip layer that require inter-layer wiring, one unified circuit generates all chip identifiers, eliminating the need for multiple wires between layers while maintaining consecutive identifier allocation.
Solution Approach 2:
The identifier setting circuit is designed as a universal component that can allocate identifiers to any number of semiconductor chips without requiring additional wires. This multi-functional circuit handles identifier generation for all chips in the multilayer device, making the wiring configuration independent of the number of chips.
3Adaptability or versatility
If different structures of semiconductor chips are used in the multilayer device, then device functionality and adaptability are improved, but achieving commonality of wire positions and structures becomes difficult
Solution Approach 1:
The patent segments the wiring system into two independent parts: a simple power supply wiring that is common to all chips, and an identifier signaling system that is handled by the centralized identifier setting circuit. This segmentation allows different chip structures to be used without requiring common wire positions, as the identifier allocation is managed separately from the physical chip interconnections.
Data Source
AI summary
Disclosed herein is a semiconductor device including: an input terminal receiving, if a preceding-stage semiconductor device is layered on a predetermined one of an upper layer and a lower layer, a bit train outputted from the preceding-stage semiconductor device; a semiconductor device identifier hold block holding a semiconductor device identifier for uniquely identifying the semiconductor device; a semiconductor device identifier computation block executing computation by using the semiconductor device identifier to update the semiconductor device identifier held in the semiconductor device identifier hold block according to a result of the computation; a control block once holding data of a bit train entered from the input terminal to control updating of the semiconductor device identifier executed by the semiconductor device identifier computation block based on the held data; and an output terminal outputting the bit train held in the control block to a succeeding-stage semiconductor device layered on another layer.