Multilayer Spiral Chip Inductor for Miniaturization and Q Value
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Solution Overview
Problem
The challenge is to achieve miniaturization of chip inductors while maintaining or improving their electrical performance, as the increasing demand for smaller electronic products requires better integration and performance from these components.
Innovation Solution
A chip inductor design featuring a multilayer plane spiral coil structure with alternating insulating and metal layers, where patterned metal structures are electrically connected through via structures, allowing for a large inductance value within a small size, manufactured using a semiconductor process to enhance precision and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of chip inductor is reduced to meet miniaturization requirements, then the integration level of electronic products is improved, but the inductance value and electrical performance deteriorate
Solution Approach 1:
The patent transitions from a planar single-layer coil structure to a three-dimensional multilayer stacked coil structure. By adding the vertical dimension through multiple layers connected by vias, the inductance value increases without increasing the planar footprint, thus achieving miniaturization while maintaining electrical performance
Solution Approach 2:
The patent embeds multiple coil structures within a compact stacked configuration where inner layers are surrounded by outer layers. This nested arrangement maximizes the use of available space, allowing multiple inductive paths to coexist in a small volume, thereby increasing total inductance while maintaining small size
2Manufacturing precision
If traditional manufacturing processes are used for chip inductor, then the manufacturing simplicity is maintained, but the size control precision and conductivity are insufficient
Solution Approach 1:
The patent replaces traditional mechanical winding and assembly processes with semiconductor-compatible deposition and patterning techniques. Metal layers are formed through sputtering or electroplating, and vias are created through photolithography and etching, enabling precise dimensional control at micrometer scales while maintaining manufacturing efficiency
Solution Approach 2:
The patent utilizes controllable deposition parameters (thickness, composition, grain structure) and patterning parameters (line width, spacing, via dimensions) to precisely adjust the electrical properties and geometric dimensions of the inductor. By optimizing these parameters, the manufacturing process achieves high precision size control and improved conductivity
3Reliability
If the number of metal layers is increased to increase inductance value, then the inductance value is improved, but the manufacturing complexity and resistance increase
Solution Approach 1:
The patent divides the continuous coil structure into discrete metal layers separated by insulating dielectric layers. Each layer is independently patterned and connected through vias, allowing modular manufacturing where each layer can be processed separately. This segmentation enables precise control of each layer's contribution to total inductance while simplifying the manufacturing of complex multilayer structures
Data Source
AI summary
Provided is a chip inductor and manufacturing method thereof. The chip inductor includes: a pin layer, a plurality of insulating layers and a plurality of metal layers, where the insulating layers and the metal layers are arranged successively and alternately on the pin layer. Multiple patterned metal structures arranged in the plurality of metal layers are respectively electrically connected to form a multilayer plane spiral coil structure. The multilayer plane spiral coil structure has two ends electrically connected with respective pin structures in the pin layer.