Multilayer Chip Stacking With Pre-Divided Wafer Alignment
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Solution Overview
Problem
Conventional methods for manufacturing multilayer devices with stacked chips, such as COW and WOW, complicate the manufacturing process due to the need for repeated stacking operations and handling of thinned semiconductor wafers, which can lead to shear stress and breakage, necessitating thermal processes to enhance joining strength.
Innovation Solution
A method involving a dividing step and a joining step where chip regions are singulated individually using plasma or laser light, allowing for direct stacking onto base regions with precise positional relationships, eliminating the need for individual handling and expansion of chip regions, and reducing the risk of contact and unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chips are stacked one by one on N base regions according to the COW method, then individual chip positioning is achieved, but the stacking operation must be performed N × M times which complicates the manufacturing process
Solution Approach 1:
The patent merges multiple individual stacking operations into a single collective stacking operation. By forming chip regions on a single semiconductor wafer that corresponds to multiple base regions, and then stacking the entire wafer at once, the process reduces stacking operations from N×M individual operations to just M collective operations, significantly simplifying the manufacturing process while maintaining precise positioning through the wafer-level correspondence
Solution Approach 2:
The patent segments the semiconductor wafer into multiple chip regions, each corresponding to a specific base region. This segmentation allows the wafer to be treated as a modular unit that can be stacked collectively while still providing individual chip-level positioning accuracy, as each chip region maintains its specific correspondence to its target base region
2Ease of operation
If thinned semiconductor wafers are stacked on a base wafer according to the WOW method, then handling difficulty increases due to fragility, but joining strength must be enhanced through thermal processes which adds process steps
Solution Approach 1:
The patent performs the thinning operation before the stacking operation, rather than after. By thinning the semiconductor wafer to the desired thickness before stacking it onto the base wafer, the process eliminates the need for subsequent thinning operations that would require complex thermal processes to prevent breakage. This preliminary thinning simplifies the overall process while maintaining wafer integrity throughout handling
Solution Approach 2:
The patent replaces the mechanical thermal processing system with a simpler process flow. Instead of using thermal processes to enhance joining strength during and after stacking, the invention uses precise mechanical positioning and control during the stacking operation itself, eliminating the need for additional thermal treatment steps
3Manufacturing precision
If chip regions are singulated individually before stacking, then precise positioning is achieved, but the risk of contact and unevenness increases during individual handling
Solution Approach 1:
The patent merges the handling of multiple chip regions into a single collective handling operation. By keeping chip regions connected on the same semiconductor wafer during handling and stacking, the process eliminates the risks associated with individual handling such as contact between chips and positioning unevenness. The entire wafer with all chip regions is handled as one unit, ensuring consistent positioning and reducing defect rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by allowing chip regions to be collectively joined in a single operation, reducing positional unevenness, and eliminating the need for thermal processes, thus enhancing manufacturing efficiency and reducing defects.
Implementation Method 1
cutting using plasma or laser light is performed on a second joining target provided with a plurality of chip regions
Implementation Method 2
cutting using plasma or laser light is performed on a second joining target provided with a plurality of chip regions
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A method of manufacturing a multilayer device performs a dividing step and a joining step before cutting is performed on a first joining target provided with a plurality of base regions while the first joining target is held by a first support. Here, the cutting is for singulating the base regions individually. In the dividing step, cutting using plasma or laser light is performed on a second joining target provided with a plurality of chip regions while the second joining target is held by a second support to form a dividing part for dividing adjacent ones of the chip regions from each other at a predetermined width therebetween. In the joining step, the second support is moved relative to the first support while the first joining target is held by the first support, thereby joining the second joining target to the first joining target in such a manner that at least one of the chip regions corresponding to each of the base regions is stacked on the corresponding base region in a predetermined positional relationship therebetween.