Multilayer Circuit Board Signal and Power Isolation
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Solution Overview
Problem
In Power over Coax (PoC) technology, the requirement for high-current supporting capability of inductor components necessitates increased size, which in turn increases the size of mounting pads on multilayer circuit boards, leading to characteristic impedance changes in microstrip lines. This creates a trade-off between the size of inductor components and the accuracy of characteristic impedance.
Innovation Solution
The solution involves forming a multilayer circuit board with a signal and power isolation circuit, where a chip inductor is mounted between a mounting pad on a microstrip line and a power supply. An inductor characteristic compensation portion and a signal transmission characteristic compensation portion are formed in the inner-layer ground to minimize characteristic impedance changes and suppress capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of the inductor component is increased to improve high-current supporting capability, then the current carrying capacity is improved, but the characteristic impedance accuracy of the microstrip line deteriorates due to increased mounting pad size
Solution Approach 1:
The patent segments the ground layer into multiple layers (first ground layer and second ground layer) positioned at different heights. By removing portions of both ground layers below the mounting pad, the solution distributes the impedance control function across multiple segmented ground structures, allowing the mounting pad to support higher currents while maintaining characteristic impedance accuracy through coordinated removal from both layers.
Solution Approach 2:
The patent transitions from a single-plane ground removal approach to a three-dimensional approach by removing ground portions from multiple layers at different heights. This vertical dimensionality addition allows independent optimization of current carrying capacity (through larger mounting pad) and impedance control (through multi-layer ground removal), resolving the trade-off between the two requirements.
2Power
If the size of the inductor component is increased to improve high-current supporting capability, then the current carrying capacity is improved, but the capacitive coupling between the inductor and ground layer increases
Solution Approach 1:
The patent extracts (removes) portions of ground from both the first and second ground layers directly below the mounting pad and inductor component. This extraction eliminates the capacitive coupling paths between the inductor and the ground layers, allowing the inductor to be sized larger for high-current support without suffering from increased capacitive coupling effects.
3Power
If the width of the mounting pad is increased to support larger inductor components, then the high-current capability is improved, but the characteristic impedance control of the microstrip line becomes more difficult
Solution Approach 1:
The patent applies local quality modification by selectively removing ground portions only in specific locations (below the mounting pad and inductor) while leaving other ground areas intact. This localized ground removal creates favorable electrical conditions specifically at the high-current mounting pad region, allowing wider pad design for high current while maintaining impedance control in the microstrip line through the localized nature of the modification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses capacitive coupling between the chip inductor and the ground layer while minimizing characteristic impedance changes in the mounting pad, thereby achieving stable signal transmission characteristics and high-current support capabilities.
Implementation Method 1
suppress the capacitive coupling between the chip inductor and the ground layer below the chip inductor
Implementation Method 2
minimize the characteristic impedance changes occurring in the mounting pad
Data Source
AI summary
A multilayer circuit board having a signal and power isolation circuit, which can suppress the capacitive coupling between a chip inductor and a ground layer below the chip inductor and also suppress the characteristic impedance change occurring in a mounting pad on a microstrip line. Portions of the inner-layer ground below both the mounting pad on the microstrip line and the chip inductors connected to the mounting pad are separately removed respectively as the signal transmission characteristic compensation removal portion, which is formed by removing a portion having a predetermined area and situated immediately below the mounting pad, and the inductor characteristic compensation removal portion, which is formed by removing a mounting-surface-below portion having a predetermined area and situated immediately below the chip inductors. The signal transmission characteristic compensation removal portion and the inductor characteristic compensation removal portion are electrically isolated from each other with the predetermined distance therebetween.